http://chineseinput.net/에서 pinyin(병음)방식으로 중국어를 변환할 수 있습니다.
변환된 중국어를 복사하여 사용하시면 됩니다.
Characteristic Graph를 利用한 組合論理回路의 故障診斷 (pp.42-49)
임인칠(Lim In Chil),이양희(Lee Yang Hi),김한우(Kim Han Yoo) 한국정보과학회 1978 정보과학회논문지 Vol.5 No.1
This paper describes test-pattern generation and it's sequence for fan out-free Combinational logic network with multiple faults. The method for detecting multiple faults, in systematic way, is established by using characteristic graphs. This method is applied even in the case of fan out-reconvergent combinational logic networks. In this case, the network is decomposed into a set of fan out-free subnetworks characteristic graphs, and minimal test patterns are generated seperately. The each test set is combined and the test pattern for fan out-reconvergent networks are derived. According to corresponding characteristic graph, additional test patterns to detect multiple faults are simply derived.
임인칠(Lim In Chil),이양희(Lee Yang Hi),김한우(Kim Han yoo) 한국정보과학회 1977 정보과학회논문지 Vol.4 No.2
In this paper, an algorithm for generating the test set to detect all multiple stuck-at-faults in multiple-output combinational logic network is presented. The algorithm represented here is the procedure to generate the test patterns by following steps; First, the circuits constituted with the overlapped paths in the multiple output circuit are conception ally considered as lines and it is the pseudo-input lines of the multiple output circuit. Next, the test patterns of the overlapped-path circuits and those of the output circuits contained the overlapped-path circuits are generated. The Algorithm is derived from the conception of pseudo inputs by using the cause-effect equation. And it is shown that the test patterns can be generated by simpler procedure than other methods and the procedure of generating minimum test patterns is derived.