Parallel PNP 및 N+ drift가 삽입된 높은홀딩전압특성을 갖는 ESD보호회로에 관한 연구

곽재창 한국전기전자학회 2020 전기전자학회논문지 Vol.24 No.3

In this paper, we propose an ESD protection device with improved electrical characteristics through structural changesof LVTSCR, a typical ESD protection device. The proposed ESD protection device has a higher holding voltage than theexisting LVTSCR by inserting a long N+ drift region and additional P-Well and N-Well, and improves the latch-upimmunity, a chronic disadvantage of a general SCR-based ESD protection device. In addition, the effective base width ofparasitic BJTs was set as a design variable, and the electrical characteristics of the proposed ESD protection device wereverified through Synopsys’ TCAD simulation so that it can be applied to the required application by applying theN-Stack technology. 본 논문에서는 대표적인 ESD 보호소자인 LVTSCR의 구조적 변화를 통해 높은 홀딩전압 특성을 가지는 ESD 보호소자를제안한다. 제안된 ESD 보호소자는 병렬 PNP path와 긴 N+ drift 영역을 삽입하여 기존의 LVTSCR보다 높은 홀딩전압을 가지며, 일반적인 SCR 기반 ESD보호소자의 단점인 Latch-up 면역특성을 향상시킨다. 또한 기생 BJT들의 유효 베이스 폭을설계변수로 설정하였으며, N-Stack 기술을 적용하여 요구되는 application에 적용할 수 있도록 시놉시스사의 TCAD 시뮬레이션을 통해 제안된 ESD 보호소자의 전기적 특성을 검증하였다.

휴대인터넷 페이징 프로토콜의 성능평가

곽재창 서경대학교 산업기술연구소 2005 産業技術硏究所論文集 Vol.16 No.-

HPi(High-speed Portable internet) is the internet infrastructure that supports high-speed mobility. The study on paging techniques for receiving IP packets in wireless high-speed internet system that provides IP packet data service is very crucial to enable mobile host to do not only dispatching service but receiving service, and contributes to enhance the techniques of wireless high-speed internet system that provides IP packet data service. The objective of this research is to design and implement a paging mechanism and its algorithm for dispatching and receiving IP packet data in HPi. In this paper, the simulation results of the proposed paging protocol are provided to evaluate the performance of the protocol.

Stack 기술을 이용한 향상된 감내 특성을 갖는SCR 기반 ESD 보호 소자에 관한 연구

곽재창 한국전기전자학회 2019 전기전자학회논문지 Vol.23 No.3

In this paper, a new ESD protection device is proposed to improve the trigger voltage and robustness. The HHVSCRand the proposed device were compared to verify the trigger voltage, the holding voltage and the robustness. The gatelength was modified to verify the electrical characteristics. The trigger voltage, the holding voltage and the robustnesswere certified by comparing the proposed device and the stacking structure. 본 논문에서는 트리거 전압과 감내 특성을 개선시키기 위해 HHVSCR의 구조적 변경을 바탕으로 Stack 기술을 적용한 새로운 ESD 보호 소자를 제안한다. 우선 HHVSCR과 제안된 ESD 보호 소자를 비교하여 트리거 전압과 홀딩 전압, 감내 특성을 확인하였고 게이트 길이에 대한 변수를 추가하였다. 마지막으로, 제안된 ESD 보호 소자와 Stack을 적용한 소자를 비교하여 트리거 전압과 홀딩 전압, 감내 특성을 비교하였다.

휴대인터넷에서의 페이징 프로토콜

곽재창 서경대학교 산업기술연구소 2004 産業技術硏究所論文集 Vol.14 No.-

HPi(High-speed Portable internet) is the internet infrastructure that supports high-speed mobility. HPi follows 802.16 and 802.16e of IEEE and the Mobile IP standard proposals of IETF. The direction of research for HPi, the next-generation wireless internet system that are currently being developed domestically, is to the reduction of development period and cost, and HPi system will fully utilize the international standard proposal and the existing wired infrastructure. Therefore, the study of paging technology in IP packet data system is indispensable and very crucial. The objective of this research is to design and implement a paging mechanism and its algorithm for dispatching and receiving IP packet data in HPi providing IP packet data services.

IP 호스트 페이징 서비스의 절차 및 방법

곽재창 서경대학교 산업기술연구소 2003 産業技術硏究所論文集 Vol.13 No.-

HPi is the internet infrastructure that supports high-speed mobility. HPi follows 802.16 and 802.16e of IEEE and the Mobile IP standard proposals of IETF, and it is being studied to add additional services such as IP packet receiving service. We analyse IP paging techniques known as the technique necessary for implementing IP packet receiving service, and propose IP paging protocol and its model for HPi system. HPi system is supposed to follow Mobile IP standards for macro mobility. The part not yet decided in Mobile IP standards is paging-related one. The processing of paging can be different depending on network system and the exterior environments of networks such that it is difficult to be standardized. In IP-based wireless communication system, the study on system as well as paging techniques suitable to the system is proceeded at the same time.

유럽 Premium IP Networks에서의 QoS 구조

곽재창 서경대학교 산업기술연구소 2002 産業技術硏究所論文集 Vol.12 No.-

On the Internet, a Quality of Service(QoS) guaranteed services are increasingly being demanded, and Differentiated Services(DiffServ) is a proposed architecture for the Internet by IETF. This overview details technical results of QoS provisioning in large IP Networks researched by the European premium IP projects. Admission control and resource control are key components for QoS delivery in IP networks because it determines the extent to which network resources are utilized and whether the contracted QoS characteristics are actually delivered. They introduce a new mechanism which provides a complete and efficient solution based on the Diffserv architecture. We analyze the proposed mechanism in terms of flexibility and assurance of QoS services, and suggest future directions.

SIMT구조 GP-GPU의 명령어 처리 성능 향상을 위한 Dispatch Unit과 Operand Selection Unit설계

곽재창,Kwak, Jae Chang 한국전기전자학회 2015 전기전자학회논문지 Vol.19 No.3

본 논문은 그래픽 처리 뿐 만 아니라 범용 연산의 가속화를 지원하기 위한 SIMT 구조 GP-GPU의 Dispatch Unit과 Operand Selection Unit을 제안한다. Warp Scheduler로부터 발행된 명령어에서 사용되는 Operand의 모든 정보를 Decoding 하면 불필요한 Operand Load가 발생하여 레지스터 부하가 발생 한다. 이러한 문제점을 해결하기 위해 Pre-decoding방법을 사용하여 Operand의 정보만을 먼저 Decoding 하여 Operand Load를 줄이고, 레지스터의 부하를 줄일 수 있는 방법을 제안한다. 제안하는 Dispatch Unit에서 나온 Operand 정보들을 레지스터 뱅크 충돌을 방지하는 방법을 적용한 Operand Selection Unit에 전달해 전체적인 처리 성능을 향상 시켰다. Modelsim 10.0b를 이용하여 Warp Scheduler로부터 발행된 10,000개의 임의의 명령어를 처리하여 소요되는 총 Clock Cycle을 측정하였다. 본 논문에서 제안한 Pre-Decoding 기능을 탑재한 Dispatch Unit과 Operand Selection Unit을 적용하여 기존의 방법들 보다 각각 약 11%, 24%의 처리 효율이 증가한 것을 확인 할 수 있었다. This paper proposes a dispatch unit of GP-GPU with SIMT architecture to support the acceleration of general-purpose operation as well as graphics processing. If all the information of an operand used instructions issued from the warp scheduler is decoded, an unnecessary operand load occurs, resulting in register loads. To resolve this problem, this paper proposes a method that can reduce the operand load and the load on the resister by decoding only the information of the operand using a pre-decoding method. The operand information from the dispatch unit is passed to the operand selection unit with preventing register bank collisions. Thus the overall performance are improved. In the simulation test, the total clock cycles required by processing 10,000 arbitrary instructions issued from the wrap scheduler using ModelSim SE 10.0b are measured. It shows that the application of the dispatch unit equipped with the pre-decoding function proposed in this paper can make an improvement of about 12% in processing performance compared to the conventional method.

래치-업 면역과 높은 감내 특성을 가지는 LIGBT 기반 ESD 보호회로에 대한 연구

곽재창,Kwak, Jae Chang 한국전기전자재료학회 2014 전기전자재료학회논문지 Vol.27 No.11

Electrostatic discharge has been considered as a major reliability problem in the semiconductor industry. ESD reliability is an important issue for these products. Therefore, each I/O (Input/Output) PAD must be designed with a protection circuitry that creates a low impedance discharge path for ESD current. This paper presents a novel Lateral Insulated Gate Bipolar (LIGBT)-based ESD protection circuit with latch-up immunity and high robustness. The proposed circuit is fabricated by using 0.18 um BCD (bipolar-CMOS-DMOS) process. Also, TLP (transmission line pulse) I-V characteristic of proposed circuit is measured. In the result, the proposed ESD protection circuit has latch-up immunity and high robustness. These characteristics permit the proposed circuit to apply to power clamp circuit. Consequently, the proposed LIGBT-based ESD protection circuit with a latch-up immune characteristic can be applied to analog integrated circuits.

주차타워 차량용 승강기 운용 알고리즘

곽재창 서경대학교 산업기술연구소 2000 産業技術硏究所論文集 Vol.8 No.-

lmprovement of an operation algorithm for an parking tower elevator system in which vehicles are entered at the lower center and stored at the vertical storage is suggested to minimize service waiting times of the parking tower. The new algorithm is simulated to analysis how much service waiting time can be reduced at various patterns of entering to the parking tower and leaving from the parking tower. Since the requested service patterns defend on tile time of day, such as more entering vehicles at the early morning and more leaving vehicles at the late afternoon, an intelligent elevator operating system is suggested to adapt flexibly to patterns of requested services.

ROI 기반 실시간 이미지 정합 알고리즘 구현

곽재창,Kwak, Jae Chang 한국전기전자학회 2015 전기전자학회논문지 Vol.19 No.4

본 논문은 임베디드 환경에서 실시간으로 동작하기 위해 이미지에 ROI를 지정하고 PROSAC 알고리즘을 적용하여 구현한 파노라마 영상 정합을 제안한다. 기존의 방식은 SURF 알고리즘이나 SIFT 알고리즘과 같이 복잡한 연산과 많은 연산 데이터의 알고리즘을 화면 전체에 적용하여 탐색한다. 또한 outlier 제거 알고리즘으로 RANSAC을 적용하여 알고리즘이 가진 무작위성으로 추가적인 검증 시간을 필요로 한다. 본 논문은 파노라마 영상의 특성을 고려하여 ROI를 설정함으로써 불필요한 연산량을 줄이고 outlier 제거 알고리즘을 검증 시간을 줄인 PROSAC 알고리즘으로 채택하여 처리 속도를 개선하였다. 비교 실험은 ARM Cortex-A15가 내장된 ODROID-XU 환경에서 진행 하였다. 제안하는 방식은 기존의 방식보다 처리 시간이 약 54% 개선되었다. This paper proposes a panoramic image stitching that operates in real time at the embedded environment by applying ROI and PROSAC algorithm. The conventional panoramic image stitching applies SURF or SIFT algorithm which contains complicated operations and a lots of data, at the overall image to detect feature points. Also it applies RANSAC algorithm to remove outliers, so that an additional verification time is required due to its randomness. In this paper, unnecessary data are eliminated by setting ROI based on the characteristics of panorama images, and PROSAC algorithm is applied for removing outliers to reduce verification time. The proposed method was implemented on the ORDROID-XU board with ARM Cortex-A15. The result shows an improvement of about 54% in the processing time compared to the conventional method.