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Brief Overview on Design Techniques and Architectures of SAR ADCs
Park, Kunwoo,Chang, Dong-Jin,Ryu, Seung-Tak The Institute of Semiconductor Engineers 2021 Journal of semiconductor engineering Vol.2 No.1
Successive Approximation Register (SAR) Analog-to-Digital Converters (ADC) seem to become the hottest ADC architecture during the past decade in implementing energy-efficient high performance ADCs. In this overview, we will review what kind of circuit techniques and architectural advances have contributed to place the SAR ADC architecture at its current position, beginning from a single SAR ADC and moving to various hybrid architectures. At the end of this overview, a recently reported compact and high-speed SAR-Flash ADC is introduced as one design example of SAR-based hybrid ADC architecture.
Han-Yeol Lee,Eunji Youn,Young-Chan Jang 대한전자공학회 2019 Journal of semiconductor technology and science Vol.19 No.4
A 10-bit 100-MS/s pipelined SAR ADC which consists of a 5-bit coarse SAR ADC with 1-bit redundancy, a dynamic amplifier for a residue amplifier, a 6-bit fine SAR ADC, and a digital error correction is proposed. One-bit redundancy generation for a digital error correction is designed using a capacitor-based DAC used in the 5-bit coarse SAR ADC for a sub-ADC of a pipelined ADC. The input range calibration and dynamic amplifier with gain compensation circuit are proposed to improve the linearity of the pipelined SAR ADC. The proposed pipelined SAR ADC has been implemented using a 65-nm 1-poly 8-metal CMOS process with a 1.2-V supply voltage. Its active area and power consumption are 410 μm × 425 μm and 4.35 mW, respectively. The measured SNDR are approximately 53.47 dB for a 2.4 Vpp differential sinusoidal input with a frequency of 9.99 MHz.
Digital Error Correction for a 10-Bit Straightforward SAR ADC
Rikan, Behnam Samadpoor,Abbasizadeh, Hamed,Do, Sung-Han,Lee, Dong-Soo,Lee, Kang-Yoon The Institute of Electronics and Information Engin 2015 IEIE Transactions on Smart Processing & Computing Vol.4 No.1
This paper proposes a 10-b SAR ADC. To increase the conversion speed and reduce the power consumption and area, redundant cycles were implemented digitally in a capacitor DAC. The capacitor DAC algorithm was straightforward switching, which included digital error correction steps. A prototype ADC was implemented in CMOS $0.18-{\mu}m$ technology. This structure consumed $140{\mu}W$ and achieved 59.4-dB SNDR at 1.25MS/s under a 1.8-V supply. The figure of merit (FOM) was 140fJ/conversion-step.
An 11-bit 160-MS/s Non-binary C-based SAR ADC with a Partially Monotonic Switching Scheme
Jae-Hyuk Lee,Jun-Ho Boo,Jun-Sang Park,Tai-Ji An,Hee-Wook Shin,Young-Jae Cho,Michael Choi,Jin-Wook Burm,Gil-Cho Ahn,Seung-Hoon Lee 대한전자공학회 2023 Journal of semiconductor technology and science Vol.23 No.2
This work proposes a single-channel 11-bit successive-approximation register (SAR) analog-to-digital converter (ADC) with an operating speed of 160-MS/s based on a non-binary digital-to-analog converter (DAC) for settling error correction. In the proposed DAC, a non-binary-weighted structure with redundancy is employed for the upper 8-bit capacitor array to reduce the residual voltage settling time requirement, facilitating high-speed operation. The remaining 3-bit capacitor array is composed of three unit capacitors, which are attached to the fractional reference voltages generated from a resistor string (R-string). The proposed partially monotonic switching scheme reduces the switching power consumption and the common-mode voltage variations of the DAC output voltage. The proposed 3D-encapsulated capacitor layout reduces the interference of adjacent signals while securing the high linearity of capacitors. Implemented in a 28 nm CMOS, the proposed ADC consumes 1.67 mW of power with a 1.0 V supply voltage and occupies an active area of 0.026 mm2. The prototype ADC achieves a signal-to-noise-and-distortion-ratio (SNDR) and a spurious-free-dynamic-range (SFDR) of 53.5 dB and 67.5 dB, with a 9 MHz input at 160 MS/s, respectively.
Mismatch-tolerant Capacitor Array Structure for Junction-splitting SAR Analog-to-digital Conversion
이영주,오태현,박인철 대한전자공학회 2017 Journal of semiconductor technology and science Vol.17 No.3
A new junction-splitting based SAR ADC with a redundant searching capacitor array structure in 0.13 μm CMOS process to alleviate capacitor mismatch effects, is presented. The normalized average power has a factor of 0.35 to the conventional SAR ADC at 10-bit conversion accuracy. Statistical experiments show the number of missing codes resulting from the mismatch reduces by 95% for 3% unit-capacitor mismatch ratio, while keeping the conversion energy to that of the conventional JS capacitor array.
Mismatch-tolerant Capacitor Array Structure for Junction-splitting SAR Analog-to-digital Conversion
Youngjoo Lee,Taehyoun Oh,In-Cheol Park 대한전자공학회 2017 Journal of semiconductor technology and science Vol.17 No.3
A new junction-splitting based SAR ADC with a redundant searching capacitor array structure in 0.13 ㎛ CMOS process to alleviate capacitor mismatch effects, is presented. The normalized average power has a factor of 0.35 to the conventional SAR ADC at 10-bit conversion accuracy. Statistical experiments show the number of missing codes resulting from the mismatch reduces by 95% for 3% unit-capacitor mismatch ratio, while keeping the conversion energy to that of the conventional JS capacitor array.
Mismatch-tolerant Capacitor Array Structure for Junction-splitting SAR Analog-to-digital Conversion
Lee, Youngjoo,Oh, Taehyoun,Park, In-Cheol The Institute of Electronics and Information Engin 2017 Journal of semiconductor technology and science Vol.17 No.3
A new junction-splitting based SAR ADC with a redundant searching capacitor array structure in $0.13{\mu}m$ CMOS process to alleviate capacitor mismatch effects, is presented. The normalized average power has a factor of 0.35 to the conventional SAR ADC at 10-bit conversion accuracy. Statistical experiments show the number of missing codes resulting from the mismatch reduces by 95% for 3% unit-capacitor mismatch ratio, while keeping the conversion energy to that of the conventional JS capacitor array.