An Input-Powered High-Efficiency Interface Circuit with Zero Standby Power in Energy Harvesting Systems

Li, Yani,Zhu, Zhangming,Yang, Yintang,Zhang, Chaolin The Korean Institute of Power Electronics 2015 JOURNAL OF POWER ELECTRONICS Vol.15 No.4

This study presents an input-powered high-efficiency interface circuit for energy harvesting systems, and introduces a zero standby power design to reduce power consumption significantly while removing the external power supply. This interface circuit is composed of two stages. The first stage voltage doubler uses a positive feedback control loop to improve considerably the conversion speed and efficiency, and boost the output voltage. The second stage active diode adopts a common-grid operational amplifier (op-amp) to remove the influence of offset voltage in the traditional comparator, which eliminates leakage current and broadens bandwidth with low power consumption. The system supplies itself with the harvested energy, which enables it to enter the zero standby mode near the zero crossing points of the input current. Thereafter, high system efficiency and stability are achieved, which saves power consumption. The validity and feasibility of this design is verified by the simulation results based on the 65 nm CMOS process. The minimum input voltage is down to 0.3 V, the maximum voltage efficiency is 99.6% with a DC output current of 75.6 μA, the maximum power efficiency is 98.2% with a DC output current of 40.4 μA, and the maximum output power is 60.48 μW. The power loss of the entire interface circuit is only 18.65 μW, among which, the op-amp consumes only 2.65 μW.

An Input-Powered High-Efficiency Interface Circuit with Zero Standby Power in Energy Harvesting Systems

Yani Li,Zhangming Zhu,Yintang Yang,Chaolin Zhang 전력전자학회 2015 JOURNAL OF POWER ELECTRONICS Vol.15 No.4

This study presents an input-powered high-efficiency interface circuit for energy harvesting systems, and introduces a zero standby power design to reduce power consumption significantly while removing the external power supply. This interface circuit is composed of two stages. The first stage voltage doubler uses a positive feedback control loop to improve considerably the conversion speed and efficiency, and boost the output voltage. The second stage active diode adopts a common-grid operational amplifier (op-amp) to remove the influence of offset voltage in the traditional comparator, which eliminates leakage current and broadens bandwidth with low power consumption. The system supplies itself with the harvested energy, which enables it to enter the zero standby mode near the zero crossing points of the input current. Thereafter, high system efficiency and stability are achieved, which saves power consumption. The validity and feasibility of this design is verified by the simulation results based on the 65 nm CMOS process. The minimum input voltage is down to 0.3 V, the maximum voltage efficiency is 99.6% with a DC output current of 75.6 μA, the maximum power efficiency is 98.2% with a DC output current of 40.4 μA, and the maximum output power is 60.48 μW. The power loss of the entire interface circuit is only 18.65 μW, among which, the op-amp consumes only 2.65 μW.

New Path-Setup Method for Optical Network-on-Chip

Huaxi Gu,Zhengyu Wang,Yintang Yang,Xiaoshan Yu 한국전자통신연구원 2014 ETRI Journal Vol.36 No.3

With high bandwidth, low interference, and low powerconsumption, optical network-on-chip (ONoC) hasemerged as a highly efficient interconnection for the futuregeneration of multicore system on chips. In this paper, wepropose a new path-setup method for ONoC to mitigatecontentions, such as packets, by recycling the setup packethalfway to the destination. A new, strictly non-blocking6 × 6 optical router is designed to support the new method. The simulation results show the new path-setup methodincreases the throughput by 52.03%, 41.94%, and 36.47%under uniform, hotspot-I, and hotspot-II traffic patterns,respectively. The end-to-end delay performance is alsoimproved.

Improved multi-recessed p-buffer 4H–SiC metal-semiconductor field-effect transistor with high power added efficiency

Zhu Shunwei,Jia Hujun,Yang Yintang 한국물리학회 2023 Current Applied Physics Vol.49 No.-

Based on the Multi-Recessed p-Buffer (MRB) Metal-Semiconductor Field-Effect Transistor (MESFET), this paper presents an Improved MRB 4H–SiC MESFET (IMRB MESFET) with high Power-Added Efficiency (PAE). The proposed structure has optimized recessed buffer layer from gate to drain. While maintaining excellent Radio Frequency performance, the maximum power density and PAE are greatly improved. The simulation results show that compared with MRB MESFET, the saturated drain current of IMRB MESFET is increased by 91.1%, the transconductance is increased by 15.5%, the Pmax is increased by 32.4%, and the PAE is increased by 40.29%. In summary, the IMRB MESFET is not only simple to manufacture, but also increases the energy conversion efficiency.

An Active Voltage Doubling Rectifier with Unbalanced-Biased Comparators for Piezoelectric Energy Harvesters

Lianxi Liu,Junchao Mu,Wenzhi Yuan,Wei Tu,Zhangming Zhu,Yintang Yang 전력전자학회 2016 JOURNAL OF POWER ELECTRONICS Vol.16 No.3

For wearable health monitoring systems, a fundamental problem is the limited space for storing energy, which can be translated into a short operational life. In this paper, a highly efficient active voltage doubling rectifier with a wide input range for micro-piezoelectric energy harvesting systems is proposed. To obtain a higher output voltage, the Dickson charge pump topology is chosen in this design. By replacing the passive diodes with unbalanced-biased comparator-controlled active counterparts, the proposed rectifier minimizes the voltage losses along the conduction path and solves the reverse leakage problem caused by conventional comparator-controlled active diodes. To improve the rectifier input voltage sensitivity and decrease the minimum operational input voltage, two low power common-gate comparators are introduced in the proposed design. To keep the comparator from oscillating, a positive feedback loop formed by the capacitor C is added to it. Based on the SMIC 0.18-μm standard CMOS process, the proposed rectifier is simulated and implemented. The area of the whole chip is 0.91×0.97 ㎟, while the rectifier core occupies only 13% of this area. The measured results show that the proposed rectifier can operate properly with input amplitudes ranging from 0.2 to 1.0V and with frequencies ranging from 20 to 3000 Hz. The proposed rectifier can achieve a 92.5% power conversion efficiency (PCE) with input amplitudes equal to 0.6 V at 200 Hz. The voltage conversion efficiency (VCE) is around 93% for input amplitudes greater than 0.3 V and load resistances larger than 20kΩ.

An Active Voltage Doubling Rectifier with Unbalanced-Biased Comparators for Piezoelectric Energy Harvesters

Liu, Lianxi,Mu, Junchao,Yuan, Wenzhi,Tu, Wei,Zhu, Zhangming,Yang, Yintang The Korean Institute of Power Electronics 2016 JOURNAL OF POWER ELECTRONICS Vol.16 No.3

For wearable health monitoring systems, a fundamental problem is the limited space for storing energy, which can be translated into a short operational life. In this paper, a highly efficient active voltage doubling rectifier with a wide input range for micro-piezoelectric energy harvesting systems is proposed. To obtain a higher output voltage, the Dickson charge pump topology is chosen in this design. By replacing the passive diodes with unbalanced-biased comparator-controlled active counterparts, the proposed rectifier minimizes the voltage losses along the conduction path and solves the reverse leakage problem caused by conventional comparator-controlled active diodes. To improve the rectifier input voltage sensitivity and decrease the minimum operational input voltage, two low power common-gate comparators are introduced in the proposed design. To keep the comparator from oscillating, a positive feedback loop formed by the capacitor C is added to it. Based on the SMIC 0.18-μm standard CMOS process, the proposed rectifier is simulated and implemented. The area of the whole chip is 0.91×0.97 mm², while the rectifier core occupies only 13% of this area. The measured results show that the proposed rectifier can operate properly with input amplitudes ranging from 0.2 to 1.0V and with frequencies ranging from 20 to 3000 Hz. The proposed rectifier can achieve a 92.5% power conversion efficiency (PCE) with input amplitudes equal to 0.6 V at 200 Hz. The voltage conversion efficiency (VCE) is around 93% for input amplitudes greater than 0.3 V and load resistances larger than 20kΩ.