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Extraction of Effective Carrier Velocity and Observation of Velocity Overshoot in Sub-40 ㎚ MOSFETs
Junsoo Kim,Jaehong Lee,Yeonam Yun,Byung-Gook Park,Jong Duk Lee,Hyungcheol Shin 대한전자공학회 2008 Journal of semiconductor technology and science Vol.8 No.2
Carrier velocity in the MOSFET channel is the main driving force for improved transistor performance with scaling. We report measurements of the drift velocity of electrons and holes in silicon inversion layers. A technique for extracting effective carrier velocity which is a more accurate extraction method based on the actual inversion charge measurement is used. This method gives more accurate result over the whole range of Vds, because it does not assume a linear approximation to obtain the inversion charge and it does not limit the range of applicable Vds. For a very short channel length device, the electron velocity overshoot is observed at room temperature in 37 ㎚ MOSFETs while no hole velocity overshoot is observed down to 36 ㎚. The electron velocity of short channel device was found to be strongly dependent on the longitudinal field.
Complete Quasi-Static Modeling of Accumulation Mode MOSFETs
Keum-Dong Jung,Yeonam Yun,Hyungcheol Shin,Byung-Gook Park,Jong Duk Lee 대한전자공학회 2007 대한전자공학회 학술대회 Vol.2007 No.11
Complete quasi-static small signal modeling for double gate accumulation MOSFETs is done in this paper. Using the shift and ratio method, the source and drain resistance is extracted and de-embeded from the Y-parameters. Accuracy of the model and extraction method was verified with the 2-D device simulation data up to 200 ㎓. The accumulation mode MOSFETs show superior RF characteristics than the general MOSFETs.
Kim, Junsoo,Lee, Jaehong,Song, Ickhyun,Yun, Yeonam,Lee, Jong Duk,Park, Byung-Gook,Shin, Hyungcheol IEEE 2008 IEEE transactions on electron devices Vol.55 No.10
<P> This paper presents a new extraction method for effective channel length <TEX Notation='TeX'> <TEX>$(L_{\rm eff})$</TEX></TEX> and source/drain series resistance <TEX Notation='TeX'><TEX>$(R_{\rm SD})$</TEX> </TEX> in ultrashort-channel MOSFETs using an iterative process, which is a modified channel resistance method (CRM). Although conventional methods for extracting <TEX Notation='TeX'><TEX>$L_{\rm eff}$</TEX></TEX> and <TEX Notation='TeX'><TEX>$R_{\rm SD}$</TEX></TEX>, such as the channel resistance and shift-and-ratio methods, are considered to be the most consistent techniques, they are not valid for shorter channel transistors, such as the total resistance <TEX Notation='TeX'><TEX>$(R_{\rm tot} = V_{\rm DS}/I_{\rm DS})$</TEX> </TEX> of MOSFETs, and do not scale proportionately with poly-gate length <TEX Notation='TeX'><TEX>$(L_{\rm poly})$</TEX></TEX>. This error results from the fact that these methods assume the effective mobility f<TEX Notation='TeX'><TEX>$(\mu_{\rm eff})$</TEX></TEX> of long- and short-channel transistors to be the same. This assumption inevitably lowers the accuracy of the extracted channel length in ultrashort-channel MOSFETs. Therefore, an improved CRM using an iterative procedure has been proposed. This iteration method takes into account the fact that mobility is degraded in shorter channel devices. By compensating for the mobility in long-channel devices, more accurate approximations for <TEX Notation='TeX'><TEX>$L_{ \rm eff}$</TEX></TEX> and <TEX Notation='TeX'><TEX>$R_{\rm SD}$</TEX></TEX> are extracted compared to conventional methods. </P>
Hee-Sauk Jhon,Jae-Hong Lee,Jaeho Lee,Byoungchan Oh,Ickhyun Song,Yeonam Yun,Byung-Gook Park,Jong-Duk Lee,Hyungcheol Shin IEEE 2009 IEEE electron device letters Vol.30 No.12
<P>In this letter, <I>f</I> <SUB>max</SUB> improvement of a circuit-level radio-frequency (RF) transistor with systematic layout variations is presented in deep-submicrometer CMOS technology. We confirmed that the circuit-level MOS transistor has a tradeoff among the extrinsic capacitive and resistive parasitics (<I>C</I> <SUB>gd</SUB>, <I>C</I> <SUB>gs</SUB>, and <I>Rg</I>) on circular gate metal layers. Furthermore, it reduces the extrinsic <I>C</I> <SUB>gd</SUB> and <I>Rg,</I> which have great effect on the RF performance, simultaneously. For qualitative analysis of the capacitive coupling, which attributed to undesired extrinsic capacitance, capacitive coupling paths were separately defined as two cases, namely, direct capacitive coupling and indirect capacitive coupling. Some of the key small-signal parameters were also extracted and compared with different types of transistors, and they show a good match with the observed trends. The proposed layout exhibits the improvement of <I>f</I> <SUB>max</SUB> up to ~ 21% without <I>fT</I> variation compared to a reference device due to reduced extrinsic <I>Rg</I> and <I>C</I> <SUB>gd</SUB> parasitics by changing the number of gate contacts and gate-to-drain interconnection lines.</P>
Low Cost CMOS LNA Design Using On-Chip Size Efficient Inductors
전희석(Hee-Sauk Jhon),송익현(Ickhyun Song),윤여남(Yeonam Yun),구민석(Minsuk Koo),정학철(Hakchul Jung),신형철(Hyungcheol Shin) 대한전자공학회 2007 대한전자공학회 학술대회 Vol.2007 No.11
This paper presents the implementation technique to reduce circuit area occupation in designing Low Noise Amplifier (LNA) using size efficient inductors. We applied vertical shunt symmetric and helical inductor to match the input and output in 2.4 ㎓ CMOS LNA to reduce the circuit area. In this paper, the case of conventional LNA using asymmetric inductor, and that of ones using vertical shunt symmetrical and helical inductor with a relatively higher number of turns have been compared in order to present a size efficient CMOS LNA design method while still retaining the circuit operation characteristics.