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Fractional-N Frequency Synthesis
Woogeun Rhee,Ni Xu,Bo Zhou,Zhihua Wang 대한전자공학회 2013 Journal of semiconductor technology and science Vol.13 No.2
This paper gives an overview of fractional-N phase-locked loops (PLLs) with practical design perspectives focusing on a △Σ modulation technique and a finite-impulse response (FIR) filtering method. Spur generation and nonlinearity issues in the △Σ fractional-N PLLs are discussed with simulation and hardware results. High-order △Σ modulation with FIR-embedded filtering is considered for low noise frequency generation. Also, various architectures of finite-modulo fractional-N PLLs are reviewed for alternative low cost design, and the FIR filtering technique is shown to be useful for spur reduction in the finite-modulo fractional-N PLL design.
Fractional-N Frequency Synthesis: Overview and Practical Aspects with FIR-Embedded Design
Rhee, Woogeun,Xu, Ni,Zhou, Bo,Wang, Zhihua The Institute of Electronics and Information Engin 2013 Journal of semiconductor technology and science Vol.13 No.2
This paper gives an overview of fractional-N phase-locked loops (PLLs) with practical design perspectives focusing on a ${\Delta}{\Sigma}$ modulation technique and a finite-impulse response (FIR) filtering method. Spur generation and nonlinearity issues in the ${\Delta}{\Sigma}$ fractional-N PLLs are discussed with simulation and hardware results. High-order ${\Delta}{\Sigma}$ modulation with FIR-embedded filtering is considered for low noise frequency generation. Also, various architectures of finite-modulo fractional-N PLLs are reviewed for alternative low cost design, and the FIR filtering technique is shown to be useful for spur reduction in the finite-modulo fractional-N PLL design.
Woogeun Rhee,Herschel Ainspan,Daniel J. Friedman,Todd Rasmus,Stacy Garvin,Clay Cranford 대한전자공학회 2008 Journal of semiconductor technology and science Vol.8 No.3
This paper describes bandwidth linearization techniques in phase-locked loop (PLL) design for common-clock serial link applications. Utilizing a continuously tunable single-input dual-path LC VCO and a constant-gain phase detector, a proposed architecture is well suited to implementing PLLs that must be compliant with standards that specify minimum and maximum allowable bandwidths such as PCI Express Gen2 or FB-DIMM applications. A prototype 4.75 to 6.1-㎓ PLL is implemented in 90-nm CMOS. Measurement results show that the PLL bandwidth and random jitter (RJ) variations are well regulated and that the use of a differentially controlled dualpath VCO is important for deterministic jitter (DJ) performance.
A 7.6 ㎽ 2 Gb/s Proximity Transmitter for Smartphone-Mirrored Display Applications
Dang Liu,Xiaofeng Liu,Woogeun Rhee,Zhihua Wang 대한전자공학회 2016 Journal of semiconductor technology and science Vol.16 No.4
This paper describes a high data rate proximity transmitter design for high resolution smartphone-mirrored display applications. A 2 Gb/s transmitter is designed with a low transmission power of –70 ㏈m/㎒ and a wide bandwidth of nearly 3 ㎓. A digital pre-correction method is employed in the transmitter to mitigate the inter-symbol interference problem. A carrier-based digital pulse shaping and a reconfigurable digital envelope generation methods are employed for robust operation by utilizing 20 phases from a 2 ㎓ phase-locked loop. A 6.5-9.5 ㎓ transmitter implemented in 65 ㎚ CMOS achieves the maximum data rate of 2 Gb/s, consuming only 7.6 ㎽ from a 1 V supply.
A 7.6 mW 2 Gb/s Proximity Transmitter for Smartphone-Mirrored Display Applications
Liu, Dang,Liu, Xiaofeng,Rhee, Woogeun,Wang, Zhihua The Institute of Electronics and Information Engin 2016 Journal of semiconductor technology and science Vol.16 No.4
This paper describes a high data rate proximity transmitter design for high resolution smartphone-mirrored display applications. A 2 Gb/s transmitter is designed with a low transmission power of -70 dBm/MHz and a wide bandwidth of nearly 3 GHz. A digital pre-correction method is employed in the transmitter to mitigate the inter-symbol interference problem. A carrier-based digital pulse shaping and a reconfigurable digital envelope generation methods are employed for robust operation by utilizing 20 phases from a 2 GHz phase-locked loop. A 6.5-9.5 GHz transmitter implemented in 65 nm CMOS achieves the maximum data rate of 2 Gb/s, consuming only 7.6 mW from a 1 V supply.
A 7.6 mW 2 Gb/s Proximity Transmitter for Smartphone-Mirrored Display Applications
Dang Liu,Xiaofeng Liu,Woogeun Rhee,Zhihua Wang 대한전자공학회 2016 Journal of semiconductor technology and science Vol.16 No.4
This paper describes a high data rate proximity transmitter design for high resolution smartphone-mirrored display applications. A 2 Gb/s transmitter is designed with a low transmission power of –70 dBm/MHz and a wide bandwidth of nearly 3 GHz. A digital pre-correction method is employed in the transmitter to mitigate the inter-symbol interference problem. A carrier-based digital pulse shaping and a reconfigurable digital envelope generation methods are employed for robust operation by utilizing 20 phases from a 2 GHz phase-locked loop. A 6.5-9.5 GHz transmitter implemented in 65 nm CMOS achieves the maximum data rate of 2 Gb/s, consuming only 7.6 mW from a 1 V supply.
Ni Xu,Yiyu Shen,Sitao Lv,Han Liu,Woogeun Rhee,Zhihua Wang 대한전자공학회 2016 Journal of semiconductor technology and science Vol.16 No.4
This paper describes a spread-spectrum clock generation method by utilizing a Δ∑ digital PLL (DPLL) which is solely based on binary phase detection and does not require a linear time-to-digital converter (TDC) or other linear digital-to-time converter (DTC) circuitry. A 1-bit high-order Δ∑ modulator and a hybrid finite-impulse response (FIR) filter are employed to mitigate the phase-folding problem caused by the nonlinearity of the bang-bang phase detector (BBPD). The Δ∑ DPLL employs a two-point modulation technique to further enhance linearity at the turning point of a triangular modulation profile. We also show that the two-point modulation is useful for the BBPLL to improve the spread-spectrum performance by suppressing the frequency deviation at the input of the BBPD, thus reducing the peak phase deviation. Based on the proposed architecture, a 3.2 ㎓ spread-spectrum clock generator (SSCG) is implemented in 65 ㎚ CMOS. Experimental results show that the proposed SSCG achieves peak power reductions of 18.5 ㏈ and 11 ㏈ with 10 ㎑ and 100 ㎑ resolution bandwidths respectively, consuming 6.34 ㎽ from a 1 V supply.
Xu, Ni,Shen, Yiyu,Lv, Sitao,Liu, Han,Rhee, Woogeun,Wang, Zhihua The Institute of Electronics and Information Engin 2016 Journal of semiconductor technology and science Vol.16 No.4
This paper describes a spread-spectrum clock generation method by utilizing a ${\Delta}{\Sigma}$ digital PLL (DPLL) which is solely based on binary phase detection and does not require a linear time-to-digital converter (TDC) or other linear digital-to-time converter (DTC) circuitry. A 1-bit high-order ${\Delta}{\Sigma}$ modulator and a hybrid finite-impulse response (FIR) filter are employed to mitigate the phase-folding problem caused by the nonlinearity of the bang-bang phase detector (BBPD). The ${\Delta}{\Sigma}$ DPLL employs a two-point modulation technique to further enhance linearity at the turning point of a triangular modulation profile. We also show that the two-point modulation is useful for the BBPLL to improve the spread-spectrum performance by suppressing the frequency deviation at the input of the BBPD, thus reducing the peak phase deviation. Based on the proposed architecture, a 3.2 GHz spread-spectrum clock generator (SSCG) is implemented in 65 nm CMOS. Experimental results show that the proposed SSCG achieves peak power reductions of 18.5 dB and 11 dB with 10 kHz and 100 kHz resolution bandwidths respectively, consuming 6.34 mW from a 1 V supply.