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Low-frequency VLSI architecture with a binary data buffer for H.264 CABAC
Gen Fujita,Makoto Saitsuji 대한전자공학회 2007 ITC-CSCC :International Technical Conference on Ci Vol.2007 No.7
In the H.264 encoding process, CABAC is a significant issue in real-time implementation, because of the difficulty involved in its parallel processing. Moreover, the number of symbols of each macroblock varies greatly. Therefore, a high clock frequency is needed to satisfy the required peak performance. In the preset paper, we proposed efficient VLSI architecture of H.264 CABAC. In the proposed architecture, by storing binary data into frame memory, the required peak performance can be reduced to 1/20, and real-time execution of HD video sequences at low clock frequencies, such as 100 ㎒, can be achieved.
Stability of Double Tearing Mode in Current Hole Configuration
takashi Tuda,Gen-Ichi Kurita,Takaaki Fujita 한국물리학회 2006 THE JOURNAL OF THE KOREAN PHYSICAL SOCIETY Vol.49 No.III
A current profile with a strong current peak on the outside of a region with almost zero current density was observed in current hole experiments. Such a profile offers the possibility of having a good stability for double tearing modes, even where two resonant surfaces exist, because no magnetohydrodynamic activity identified for a double tearing mode was observed. We examine the stability of a double tearing mode for a current profile with a strong peak around an inner resonant surface and show that the profile is stable for a double tearing mode if the peak exists inside of the surface. This fact shows the possibility of stabilizing a double tearing mode by a localized co-drive current.
VLSI Implementation of Edge Detector and Vector Quantizer for Very Low Bitrate Video Encoding
Miyanohana, Koji,Fujita, Gen,Onoye, Takao,Shirakawa, Isao 대한전자공학회 1996 APCCAS:Asia Pacific Conference on Circuits And Sys Vol.1 No.1
A VLSI video encoder core is implemented dedicatedly for a very low bitrate coding, with the main theme focused on an edge detector and a vector quantizer. A new mechanism is devised so as to seek horizontal and vertical edges simultaneously, which can achieve a high throughput for the edge detector. A new scheme is also introduced into the PE (Processing Element) array so as to be shared by the vector quantizer and the motion estimator. Owing to these sophisticated concepts, specific functional macrocells have been implemented for the edge detector and vector quantizer in the total area of 55.3㎟ by a 0.6㎛ triple-metal CMOS technology.