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Modeling and Prediction of Electromagnetic Immunity for Integrated Circuits
Bo Pu,Taeho Kim,SungJun Kim,SoYoung Kim,Wansoo Nah 한국전자파학회JEES 2013 Journal of Electromagnetic Engineering and Science Vol.13 No.1
An equivalent model has been developed to estimate the electromagnetic immunity for integrated circuits under a complex electromagnetic environment. The complete model is based on the characteristics of the equipment and physical configuration of the device under test (DUT) and describes the measurement setup as well as the target integrated circuits under test, the corresponding package, and a specially designed printed circuit board. The advantage of the proposed model is that it can be applied to a SPICE-like simulator and the immunity of the integrated circuits can be easily achieved without costly and time-consuming measurements. After simulation, measurements were performed to verify the accuracy of the equivalent model for immunity prediction. The improvement of measurement accuracy due to the added effect of a bi-directional coupler in the test setup is also addressed.
Pu Bo Li,Ti Jun Chen,Su Qing Zhang 대한금속·재료학회 2017 METALS AND MATERIALS International Vol.23 No.1
The present investigation addresses a new technology, named powder thixoforming, used to fabricate SiCp/ 2024 Al-based composites. The effects of reheating time on microstructure and mechanical properties have been studied. The results indicated that the quantity of liquid, the coarsening behavior of the primary particles, the subsequent plastic deformation occurring during thixoforging, and thus the resulting microstructural compactness and mechanical properties changed as a function of reheating time. The best comprehensive tensile properties of the composite, that is an ultimate tensile strength of 370 MPa and an elongation of 4.4%, were obtained after reheating for 80 min at 625 °C, which was an increase of 23.3% and a decrease of 57.7%, respectively, compared to the 2024 alloy thixoforged under the same conditions as the composite. The fracturing in the composites occurred through interconnecting cracked SiCp and debonded SiC/Al interfaces caused by a higher concentration of stress and a coalescence of microvoids.
Electrical Parameter Extraction of High Performance Package Using PEEC Method
Bo Pu,June-Sang Lee,Wansoo Nah 한국전자파학회JEES 2011 Journal of Electromagnetic Engineering and Science Vol.11 No.1
This paper proposes a novel electrical characterization approach for a high-performance package system using an improved Partial Element Equivalent Circuit (PEEC). As the effect of interconnects becomes a pivotal factor for the performance of high-speed electronic systems, there is a great demand for an accurate equivalent model for interconnects. In particular, an equivalent model of interconnects is established in this paper for the Fine-Pitch Ball Grid Array (FBGA) package using the improved PEEC method. Based on the equivalent model, electrical characteristics are analyzed; furthermore, these are verified through the measurement results of a Vector Network Analyzer (VNA).
Modeling and Parameter Extraction of Coplanar Symmetrical Meander Lines
Bo Pu,Kwang Ho Kim,SoYoung Kim,Wansoo Nah [Institute of Electrical and Electronics Engineers 2015 IEEE transactions on electromagnetic compatibility Vol.57 No.3
<P>In this paper, a coplanar symmetrical meander line structure is presented, and an equivalent circuit model is proposed to allow estimation of its electrical characteristics based on numerical modeling. The parasitic couplings in the proposed structure are considerably different from those of a simple meander line with a ground structure below it. Analysis and derivation of inductive and capacitive couplings and of resistance in the effective frequency band are addressed in detail, and the effects of geometrical parameters on the electrical characteristics are also demonstrated. The validity of the proposed equivalent circuit model is verified by both commercial electromagnetic simulator and measurement of the scattering parameters in the frequency domain, as well as of the reflected and transmitted waveforms in the time domain. Because the proposed model is easily coded, and takes little time to compute the parameters, it is very useful in the design of inductance and capacitance in circuits on substrate, which can be used for the design of time-delay elements and stop band filters in power delivery lines.</P>
Handy Calibration Substrate for both Horizontal and Vertical Probing
Bo Pu,Taeho Kim,Jinho Joo,Wansoo Nah 대한전자공학회 2021 Journal of semiconductor technology and science Vol.21 No.2
This article proposes a novel substrate for a handy SG-GS/SG-SG calibration in both horizontal and vertical probing measurement. The proposed substrate provides two ways of probing for “through” calibration in horizontal and vertical positions without changing the probe holders. It has “through” lines vertically and horizontally using vias and traces, respectively, and both “through” lines were designed to satisfy 50 ohms of characterization impedance. A prototype of the proposed substrate was fabricated using FR4 and then tested in the horizontal calibration resulting in the successful reproduction of all the S-parameters in the horizontal meander test board. It was also tested in the vertical calibration, and was successful to re-produce all the coupling effects in via arrays, demonstrating the effectiveness and handiness of the proposed calibration substrate.
A De-Embedding Technique of a Three-Port Network with Two Ports Coupled
Bo Pu,Jonghyeon Kim,Wansoo Nah 한국전자파학회JEES 2015 Journal of Electromagnetic Engineering and Science Vol.15 No.4
A de-embedding method for multiport networks, especially for coupled odd interconnection lines, is presented in this paper. This method does not require a conversion from S-parameters to T-parameters, which is widely used in the de-embedding technique of multiport networks based on cascaded simple two-port relations, whereas here, we apply an operation to the S-matrix to generate all the uncoupled and coupled coefficients. The derivation of the method is based on the relations of incident and reflected waves between the input of the entire network and the input of the intrinsic device under test (DUT). The characteristics of the intrinsic DUT are eventually achieved and expressed as a function of the S-parameters of the whole network, which are easily obtained. The derived coefficients constitute ABCD-parameters for a convenient implementation of the method into cascaded multiport networks. A validation was performed based on a spice-like circuit simulator, and this verified the proposed method for both uncoupled and coupled cases.
Estimation of Transferred Power from a Noise Source to an IC with Forwarded Power Characteristics
Bo Pu,Taeho Kim,SungJun Kim,Jong-hyeon Kim,SoYoung Kim,Wansoo Nah 한국전자파학회JEES 2013 Journal of Electromagnetic Engineering and Science Vol.13 No.4
This paper proposes an accurate approach for predicting transferred power from a noise source to integrated circuits based on the characteristics of the power transfer network. A power delivery trace on a package and a printed circuit board are designed to transmit power from an external source to integrated circuits. The power is demonstrated between an injection terminal on the edge of the printed circuit board and integrated circuits, and the power transfer function of the power distribution network is derived. A two-tier calibration is applied to the test, and scattering parameters of the network are measured for the calculation of the power transfer function. After testing to obtain the indispensable parameters, the real received and tolerable power of the integrated circuits can be easily achieved. Our proposed estimation method is an enhancement of the existing the International Electrotechnical Commission standard for precise prediction of the electromagnetic immunity of integrated circuits.
PEEC를 이용한 패커지/보드 인터커넥트 의 전기적 특성 분석
푸보(Bo Pu),이준상(Jung-sang Lee),김종민(Jongmin Kim),나완수(Wansoo Nah) 대한전기학회 2010 대한전기학회 학술대회 논문집 Vol.2010 No.7
패키지/보드, 인터커넥트를 포함한 전기회로에는 많은 기생 인덕턴스, 커패시턴스가 존재하고, 회로의 동작 주파수가 올라갈수록 이것의 영향이 커지면서 신호의 전달에 많은 영향을 미치게 된다. 회로 설계자는, 회로를 실제로 제작하기 전에, 이러한 영향을 설계 단계에서 파악하여 그 영향을 예상하여, 그 정도의 많고 적음에 따라서 대책을 강구해야 한다. 본 연구에서는 PEEC (Partial Element Equivalent Circuit) 방법을 이용하여 설계된 회로의 응답특성을 예측하는 과정을 기술한다. 예측된 신호는 실제로 제작되어 측정된 신호와 비교하여 그 방법의 타당성을 보였다.