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파워 모듈 패키지 내부 본딩 와이어의 전기적 거동 해석
배근영(GeunYoung Bae),추지연(JiYeon Choo),이범수(BumSu Lee),임진수(JinSoo Lim),유찬세(Chan-Sei Yoo) 대한전자공학회 2023 대한전자공학회 학술대회 Vol.2023 No.6
The experiment in this paper was conducted based on the actual system in package power module. Analysis of the parasitic inductance and Q factor as a simulation result aims to propose an appropriate bonding wire configuration. As a result, it was confirmed that the parasitic inductance decreased as the number of bonding wires increased. However, since performance is not proportional to the number of wires, economic feasibility must be considered. Therefore, it can be concluded that the module applied to the simulation has the most appropriate performance when there are three bonding wires. As much as the actual module is applied, the result is expected to be helpful in the design of bonding wires and manufacturing process of system in package.
Power MOSFET 패키징 성분에 따른 스위칭 회로 손실 분석
추지연(JiYeon Choo),배근영(GeunYoung Bae),이범수(BumSu Lee),유찬세(Chan-Sei Yoo) 대한전자공학회 2023 대한전자공학회 학술대회 Vol.2023 No.6
In semiconductor packaging, parasitic components generated during power MOSFET packaging affect power loss. Therefore, research should be conducted in the direction of reducing losses caused by parasitic components using techniques such as wire bonding. In this paper, the loss that occurs in the actual switching circuit when packaging a MOSFET device is quantitatively identified and compared. Analyze losses when packaging power MOSFETs occur. Parasitic components of power MOSFET packaging at switching frequencies are applied to the circuit and analyzed through simulation. In the packaging structure proposed in this paper, parasitic inductance generated during wire bonding is analyzed. When the number of wires in the power MOSFET packaging of the switching circuit is increased from 1 to 4, the losses are 58.59W, 42.72W, 37.43W, and 34.04W. Therefore, when packaging the power MOSFET, the number of bonding wires is suggested to be two.