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RB 복소수 필터를 이용한 적응 결정귀환 등화기 구조 및 칩셋 설계
김호하,안병규,신경욱,Kim, Ho Ha,An, Byeong Gyu,Sin, Gyeong Uk 한국통신학회 1999 韓國通信學會論文誌 Vol.24 No.12
디지털 통신 시스템의 기저대역 신호처리를 효율적으로 구현하기 위한 새로운 복소수 필터구조를 제안하고, 이를 적용하여 채널등화용 적응 결정귀환 등화기 (Adaptive Decision-Feedback Equalizer; ADFE) 칩셋을 설계하였다. 새로운 복소수 필터구조는 기존의 2의 보수 대신에 redundant binary (RB) 수치계를 적용한 효율적인 복소수 승산 및 누적연산을 바탕으로 한다. 제안된 방법을 적용하면, N-탭 복소수 필터는 2N개의 RB 승산기와 2N-2개의 RB 가산기로 구현되며, 필터 탭 당 Tm,RB+Ta,RB (단, Tm,RB, Ta,RB는 각각 RB 승산기 및 가산기의 지해 고속동작이 가능하다. 제안된 방법을 적용하여 설계된 ADFE는 FFEM (Feed-Foreward Equalizer Module)과 DFEM (Decision-Feedback Equalizer Module)로 구성되며, 필요에 따라 필터 탭을 확장할 수 있도록 설계되었다. 2-탭 복소수 필터, LMS 계수갱신 회로 및 부가회로 등으로 구성되는 각 모듈은 COSSAP과 VHDL을 이용한 모델링 및 검증과정을 거쳐 0.8-㎛ SOG (Sea-Of-Gate) 셀 라이브러리를 사용하여 논리합성 되었으며, 26,000여개의 게이트로 구성된다. Presented in this paper are a new complex-umber filter architecture, which is suitable for an efficient implementation of baseband signal processing of digital communication systems, and a chip-set design of adaptive decision-feedback equalizer (ADFE) employing the proposed structure. The basic concept behind the approach proposed in this paper is to apply redundant binary (RB) arithmetic instead of conventional 2’s complement arithmetic in order to achieve an efficient realization of complex-number multiplication and accumulation. With the proposed way, an N-tap complex-number filter can be realized using 2N RB multipliers and 2N-2 RB adders, and each filter tap has its critical delay of $T_{m.RB}+T_{a.RB}$ (where $T_{m.RB}, T_{a.RB}$are delays of a RB multiplier and a RB adder, respectively), making the filter structure simple, as well as resulting in enhanced speed by means of reduced arithmetic operations. To demonstrate the proposed idea, a prototype ADFE chip-set, FFEM (Feed-Forward Equalizer Module) and DFEM (Decision-Feedback Equalizer Module) that can be cascaded to implement longer filter taps, has been designed. Each module is composed of two complex-number filter taps with their LMS coefficient update circuits, and contains about 26,000 gates. The chip-set was modeled and verified using COSSAP and VHDL, and synthesized using 0.8- μm SOG (Sea-Of-Gate) cell library.
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Radix-4 Booth Recoding과 RB 연산을 이용한 새로운 복소수 승산 알고리듬 및 10-bit CMAC코어 설계
김호하,신경욱 대한전자공학회 1998 電子工學會論文誌, C Vol.c35 No.9
고속 복소수 연산장치는 채널등화, 동기신호 복원, 변조 및 복조 등 디지탈 통신 시스템의 기저대역 신호처리에 필수적인 기능블록이다. 본 논문에서는 redundant binary (RB) 연산과 radix-4 Booth recoding을 결합한 새로운 복소수 승산 알고리듬을 제안한다. 제안되는 복소수 승산 방법은 실수 승산기를 사용하는 기존의 방법과 비교하여 부분곱의 수를 반으로 감소시키며, 단순화된 병렬구조로 구현되므로 고속 동작 및 저전력 소모를 가능하게 한다. 제안된 알고리듬을 적용하여 10-bit operand를 갖는 prototype 복소수 승산-누적기(complex-number multiplier-accumulator ; CMAC) 코어를 0.8-㎛ N-Well CMOS 공정으로 설계, 제작하였다. 제작된 CMAC 칩은 18,000여개의 트랜지스터로 구성되며, 코어부분의 면적은 약 1.60 × 1.93 ㎟이다. 제작된 칩을 테스트 보드에 실장하여 특성을 평가한 결과, 전원전압 V/sub DD/=3.3-V에서 120-MHz의 속도로 동작함을 확인하였으며, 이때의 전력소모는 약 63-mW로 측정되었다. High-speed complex-number arithmetic units are essential to baseband signal processing of modern digital communication systems such as channel equalization, timing recovery, modulation and demodulation. In this paper, a new complex-number multiplication algorithm is proposed, which is based on redundant binary (RB) arithmetic combined with radix-4 Booth recoding scheme. The proposed algorithm reduces the number of partial product by one-half as compared with the conventional direct method using real-number multipliers and adders. It also leads to a highly parallel architecture and simplified circuit, resulting in high-speed operation and low power dissipation. To demonstrate the proposed algorithm, a prototype complex-number multiplier-accumulator (CMAC) core with 10-bit operands has been designed using 0.8-$\mu\textrm{m}$ N-Well CMOS technology. The designed CMAC core contains about 18,000 transistors on the area of about 1.60 ${\times}$ 1.93 $\textrm{mm}^2$. The functional and speed test results show that it can operate with 120-MHz clock at V$\sub$DD/=3.3-V, and its power consumption is given to about 63-mW.
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김태원,신경욱,김호하 金烏工科大學校 1997 論文集 Vol.18 No.-
A 10-bit complex-number multiplier-accumulator (CMAC) has been designed using 0.8-㎛ CMOS technology, which can be used as an arithmetic core for the baseband signal processing of modern digital communication systems. To achieve high-speed operation as well as low-power dissipation, a new vector multiplication algorithm is proposed, which is based on radix-4 Booth recoding scheme and redundant binary (RB) arithmetic. The proposed algorithm reduces the arithmetic complexity by half as compared with the conventional direct method that is based on real-number multipliers and adders. It leads to a highly parallel architecture with modularity and a simplified circuit, resulting in fast operation and low power dissipation. The designed CMAC core contains about 18,000 transistors on the area of about 1.60×1.93㎟. The HSPICE simulation results show that the CMAC core can safely operate with 200-MHz clock at VDD=3.3-V, and it's estimated power dissipation is about 50-mW.
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신경욱,안병규,김호하 金烏工科大學校 1998 論文集 Vol.19 No.-
This work describes an ASIC implementation of adaptive decision-feedback equalizer (ADFE) which is applicable to wide band digital wireless modems. A new approach based on redundant binary (RB) arithmetic is devised for an efficient implementation of complex-number filter which is a key functional block of ADFE. The proposed RB complex-number filter structure reduces the critical path delay of ADFE. as well as leads to a more compact realization than conventional methods. Also, the carry-propagation free (CPF) operations of the RB arithmetic enhance its speed. To demonstrate the proposed approach, a prototype chip set which is composed of feed-forward equalizer module (FFEM) and decision-feedback equalizer module (DFEM) has been designed. Each module contains two complex-number filter taps along with their coefficient update circuits, and can be cascaded to implement longer filter taps for high bit-rate applications. The chip set was modeled and verified using VHDL. and synthesized using 0.8-㎛ sea-of-gate (SOG) array library.
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