Structured Pruning of Deep Convolutional Neural Networks

Anwar, Sajid,Hwang, Kyuyeon,Sung, Wonyong Association for Computing Machinery 2017 ACM journal on emerging technologies in computing Vol.13 No.3

<P>Real-time application of deep learning algorithms is often hindered by high computational complexity and frequent memory accesses. Network pruning is a promising technique to solve this problem. However, pruning usually results in irregular network connections that not only demand extra representation efforts but also do not fit well on parallel computation. We introduce structured sparsity at various scales for convolutional neural networks: feature map-wise, kernel-wise, and intra-kernel strided sparsity. This structured sparsity is very advantageous for direct computational resource savings on embedded computers, in parallel computing environments, and in hardware-based systems. To decide the importance of network connections and paths, the proposed method uses a particle filtering approach. The importance weight of each particle is assigned by assessing the misclassification rate with a corresponding connectivity pattern. The pruned network is retrained to compensate for the losses due to pruning. While implementing convolutions as matrix products, we particularly show that intra-kernel strided sparsity with a simple constraint can significantly reduce the size of the kernel and feature map tensors. The proposed work shows that when pruning granularities are applied in combination, we can prune the CIFAR-10 network by more than 70% with less than a 1% loss in accuracy.</P>

Walking improves your cognitive map in environments that are large-scale and large in extent

Ruddle, Roy A.,Volkova, Ekaterina,Bü,lthoff, Heinrich H. Association for Computing Machinery 2011 ACM transactions on computer-human interaction Vol.18 No.2

<P>This study investigated the effect of body-based information (proprioception, etc.) when participants navigated large-scale virtual marketplaces that were either small (Experiment 1) or large in extent (Experiment 2). Extent refers to the size of an environment, whereas scale refers to whether people have to travel through an environment to see the detail necessary for navigation. Each participant was provided with full body-based information (walking through the virtual marketplaces in a large tracking hall or on an omnidirectional treadmill), just the translational component of body-based information (walking on a linear treadmill, but turning with a joystick), just the rotational component (physically turning but using a joystick to translate) or no body-based information (joysticks to translate and rotate). In large and small environments translational body-based information significantly improved the accuracy of participants' cognitive maps, measured using estimates of direction and relative straight line distance but, on its own, rotational body-based information had no effect. In environments of small extent, full body-based information also improved participants' navigational performance. The experiments show that locomotion devices such as linear treadmills would bring substantial benefits to virtual environment applications where large spaces are navigated, and theories of human navigation need to reconsider the contribution made by body-based information, and distinguish between environmental scale and extent.</P>

Socio-cognitive aspects of interoperability : Understanding communication task environments among different organizations

Kwon, Gyu Hyun,Smith-Jackson, Tonya L.,Bostian, Charles W. Association for Computing Machinery 2011 ACM transactions on computer-human interaction Vol.18 No.4

<P>Emergency communication systems (ECS) are a key element in collaborations among different public safety organizations. The need for interoperability in emergency communication systems has hastened the development of interoperable communication technology that is an enabling technology to automatically identify environmental variables including appropriate radio frequencies and to connect different networks used by different organizations. Even though the technology has been researched from many perspectives and has shown that is possible to connect different organizations, there still remain many issues in terms of socio-cognitive aspects. Thus, this study examines the socio-cognitive dimensions of interoperability, which equal the technical dimensions of the problem in importance. The existential-phenomenological study reported here used semistructured interviews to reconceptualize interoperability in the public safety communication domain. Based on 11 interviews with public safety workers, five important factors were identified that have a major impact on the effectiveness of interoperable groups: information sharedness, operational awareness, communication readiness, adaptiveness, and coupledness. Based on these main concepts, high-level suggestions are provided to guide the design of a new public safety communication system. The results can be directly applied to identify the requirements of communication systems and can be extended to design collaboration systems under stressful environments.</P>

High-Performance Ideal Lattice-Based Cryptography on 8-Bit AVR Microcontrollers

Liu, Zhe,Pö,ppelmann, Thomas,Oder, Tobias,Seo, Hwajeong,Roy, Sujoy Sinha,Gü,neysu, Tim,Großschä,dl, Johann,Kim, Howon,Verbauwhede, Ingrid Association for Computing Machinery 2017 ACM transactions on embedded computing systems Vol.16 No.4

<P>Over recent years lattice-based cryptography has received much attention due to versatile average-case problems like Ring-LWE or Ring-SIS that appear to be intractable by quantum computers. In this work, we evaluate and compare implementations of Ring-LWE encryption and the bimodal lattice signature scheme (BLISS) on an 8-bit Atmel ATxmega128 microcontroller. Our implementation of Ring-LWE encryption provides comprehensive protection against timing side-channels and takes 24.9ms for encryption and 6.7ms for decryption. To compute a BLISS signature, our software takes 317ms and 86ms for verification. These results underline the feasibility of lattice-based cryptography on constrained devices.</P>

DeepToF : off-the-shelf real-time correction of multipath interference in time-of-flight imaging

Marco, Julio,Hernandez, Quercus,Muñ,oz, Adolfo,Dong, Yue,Jarabo, Adrian,Kim, Min H.,Tong, Xin,Gutierrez, Diego Association for Computing Machinery 2017 ACM transactions on graphics Vol. No.

<P>Time-of-flight (ToF) imaging has become a widespread technique for depth estimation, allowing affordable off-the-shelf cameras to provide depth maps in real time. However, multipath interference (MPI) resulting from indirect illumination significantly degrades the captured depth. Most previous works have tried to solve this problem by means of complex hardware modifications or costly computations. In this work, we avoid these approaches and propose a new technique to correct errors in depth caused by MPI, which requires no camera modifications and takes just 10 milliseconds per frame. Our observations about the nature of MPI suggest that most of its information is available in image space; this allows us to formulate the depth imaging process as a spatially-varying convolution and use a convolutional neural network to correct MPI errors. Since the input and output data present similar structure, we base our network on an autoencoder, which we train in two stages. First, we use the encoder (convolution filters) to learn a suitable basis to represent MPI-corrupted depth images; then, we train the decoder (deconvolution filters) to correct depth from synthetic scenes, generated by using a physically-based, time-resolved renderer. This approach allows us to tackle a key problem in ToF, the lack of ground-truth data, by using a large-scale captured training set with MPI-corrupted depth to train the encoder, and a smaller synthetic training set with ground truth depth to train the decoder stage of the network. We demonstrate and validate our method on both synthetic and real complex scenarios, using an off-the-shelf ToF camera, and with only the captured, incorrect depth as input.</P>

SoIoT : Toward A User-Centric IoT-Based Service Framework

Ko, In-Young,Ko, Han-Gyu,Molina, Angel Jimenez,Kwon, Jung-Hyun Association for Computing Machinery 2016 ACM transactions on Internet technology Vol.16 No.2

<P>An emerging issue in urban computing environments is the seamless selection, composition, and delivery of user-centric services that run over what is known as the Internet of Things (IoT). This challenge is about enabling services actuated by IoT devices to be delivered spontaneously from the perspective of users. To accomplish this goal, we propose the Service-Oriented Internet of Things (SoIoT), a user-centric IoT-based service framework, which integrates services that utilize IoT resources in an urban computing environment. This framework provides a task-oriented computing approach that enables the composition of IoT-based services in a spontaneous manner to accomplish a user task. Tasks can also be recommended to users based on the available IoT resources in an environment and on the contextual knowledge that is represented and managed in social, spatial, and temporal aspects. These tasks are then bound to a set of service instances and performed in a distributed manner. This final composition ensures the Quality of Service (QoS) requirements of the tasks and is assigned to multiple client devices for the efficient utilization of IoT resources. We prove the practicality of our approach by showing a real-case service scenario implemented in our IoT-based test-bed as well as experimental results.</P>

Regularities considered harmful : forcing randomness to memory accesses to reduce row buffer conflicts for multi-core, multi-bank systems

Park, Heekwon,Baek, Seungjae,Choi, Jongmoo,Lee, Donghee,Noh, Sam H. Association for Computing Machinery 2013 ACM SIGPLAN notices Vol.48 No.4

Architectural Supports to Protect OS Kernels from Code-Injection Attacks and Their Applications

Moon, Hyungon,Lee, Jinyong,Hwang, Dongil,Jung, Seonhwa,Seo, Jiwon,Paek, Yunheung Association for Computing Machinery 2017 Transactions on Design Automation of Electronic Sy Vol.23 No.1

<P>The kernel code injection is a common behavior of kernel-compromising attacks where the attackers aim to gain their goals by manipulating an OS kernel. Several security mechanisms have been proposed to mitigate such threats, but they all suffer from non-negligible performance overhead. This article introduces a hardware reference monitor, called Kargos, which can detect the kernel code injection attacks with nearly zero performance cost. Kargos monitors the behaviors of an OS kernel from outside the CPU through the standard bus interconnect and debug interface available with most major microprocessors. By watching the execution traces and memory access events in the monitored target system, Kargos uncovers attempts to execute malicious code with the kernel privilege. On top of this, we also applied the architectural supports for Kargos to the detection of ROP attacks. KS-Stack is the hardware component that builds and maintains the shadow stacks using the existing supports to detect this ROP attacks. According to our experiments, Kargos detected all the kernel code injection attacks that we tested, yet just increasing the computational loads on the target CPU by less than 1% on average. The performance overhead of the KS-Stack was also less than 1%.</P>

Predictability for timing and temperature in multiprocessor system-on-chip platforms

Thiele, Lothar,Schor, Lars,Bacivarov, Iuliana,Yang, Hoeseok Association for Computing Machinery 2013 ACM transactions on embedded computing systems Vol.12 No.s1

Designing on-chip networks for throughput accelerators

Bakhoda, Ali,Kim, John,Aamodt, Tor M. Association for Computing Machinery 2013 ACM transactions on architecture and code optimiza Vol.10 No.3

<P>As the number of cores and threads in throughput accelerators such as Graphics Processing Units (GPU) increases, so does the importance of on-chip interconnection network design. This article explores throughput-effective Network-on-Chips (NoC) for future compute accelerators that employ Bulk-Synchronous Parallel (BSP) programming models such as CUDA and OpenCL. A hardware optimization is 'throughput effective' if it improves parallel application-level performance per unit chip area. We evaluate performance of future looking workloads using detailed closed-loop simulations modeling compute nodes, NoC, and the DRAM memory system. We start from a mesh design with bisection bandwidth balanced to off-chip demand. Accelerator workloads tend to demand high off-chip memory bandwidth which results in a many-to-few traffic pattern when coupled with expected technology constraints of slow growth in pins-per-chip. Leveraging these observations we reduce NoC area by proposing a 'checkerboard' NoC which alternates between conventional full routers and half routers with limited connectivity. Next, we show that increasing network terminal bandwidth at the nodes connected to DRAM controllers alleviates a significant fraction of the remaining imbalance resulting from the many-to-few traffic pattern. Furthermore, we propose a 'double checkerboard inverted' NoC organization which takes advantage of channel slicing to reduce area while maintaining the performance improvements of the aforementioned techniques. This organization also has a simpler routing mechanism and improves average application throughput per unit area by 24.3%.</P>