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RISS 인기검색어
- 검색키워드
- 저자 : Nur A. Touba (검색결과 3 건)
- 무료
- 기관 내 무료
- 유료
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Test Point Insertion with Control Point by Greater Use of Existing Functional Flip-Flops
양준성,Nur A. Touba 한국전자통신연구원 2014 ETRI Journal Vol.36 No.6
This paper presents a novel test point insertion (TPI)method for a pseudo-random built-in self-test (BIST) toreduce the area overhead. Recently, a new TPI method forBISTs was proposed that tries to use functional flip-flopsto drive control test points instead of adding extradedicated flip-flops for driving control points. Thereplacement rule used in a previous work has limitationspreventing some dedicated flip-flops from being replacedby functional flip-flops. This paper proposes a logic coneanalysis–based TPI approach to overcome the limitations. Logic cone analysis is performed to find candidatefunctional flop-flops for replacing dedicated flip-flops. Experimental results indicate that the proposed methodreduces the test point area overhead significantly withminimal loss of testability by replacing the dedicated flipflops.
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Enhancing Test Compression With Dependency Analysis for Multiple Expansion Ratios
Taehee Lee,Touba, Nur A.,Joon-Sung Yang IEEE 2017 IEEE transactions on computer-aided design of inte Vol.36 No.9
<P>Scan test data compression is widely used in industry to reduce test data volume (TDV) and test application time (TAT). This paper shows how multiple scan chain expansion ratios can help to obtain high test data compression in system-on-chips. Scan chains are partitioned with a higher expansion ratio than normal in scan compression mode and then are gradually con-catenated based on a cost function to detect any faults that could not be detected at the higher expansion ratios. It improves the overall test compression ratio since it potentially allows faults to be detected at the highest expansion ratio. This paper introduces a new cost function to choose scan chain concatenation candidates for concatenation for multiple expansion ratios. To avoid TDV and TAT increase by scan concatenation, the proposed method takes a logic structure and scan chain length into consideration. Experiment results show the proposed method reduces TAT and TDV by 53%-64% compared with a traditional scan compression method.</P>
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Exploiting Unused Spare Columns and Replaced Columns to Enhance Memory ECC
Hyunseung Han,Touba, Nur A.,Joon-Sung Yang IEEE 2017 IEEE transactions on computer-aided design of inte Vol.36 No.9
<P>Due to the emergence of extremely high density memory along with the growing number of embedded memories, memory yield is an important issue. Memory self-repair using redundancies to increase the yield of memories is widely used. Because high density memories are vulnerable to soft errors, memory error correction code (ECC) plays an important role in memory design. In this paper, methods to exploit spare columns including replaced defective columns are proposed to improve memory ECC. To utilize replaced defective columns, the defect information needs to be stored. Two approaches to store defect information are proposed-one is to use a spare column and the other is to use a content-addressable-memory. Experimental results show that the proposed method can significantly enhance the ECC performance.</P>
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