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RISS 인기검색어
- 검색키워드
- 저자 : Meena Panchore (검색결과 3 건)
- 무료
- 기관 내 무료
- 유료
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Aging Mechanism of p-Type Dopingless JLFET: NBTI and Channel-Hot-Carrier Stress
Meena Panchore,Chithraja Rajan 한국전기전자재료학회 2023 Transactions on Electrical and Electronic Material Vol.24 No.2
In this work, an extensive study of the aging mechanisms of the p-type dopingless JLFET (DL JLFET) structure is reported for the first time. The negative-bias-temperature-instability (NBTI) and channel-hot-carrier (CHC) stress conditions are considered for analyzing the aging behavior of p-type DL JLFET. The variations in electrical characteristics of lightly doped DL JLFET are compared with its conventional counterpart JLFET against NBTL and CHC stress. We have shown that JLFET with heavily doped channel region exhibits higher drain current degradation under CHC stress due to high electric field and large gate leakage current. The JLFET has 19% drain current degradation due to CHC stress which is 1.7 times higher than DL JLFET. However, under NBTI stress, the DL JLFET has slightly higher drain current degradation and almost symmetric shift in Vth than JLFET. Hence, this study suggests that dopingless devices are superior candidate for designing aging-resilient and more reliable circuits.
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Heterogenous Gate Dielectric DLTFET: Reliability Perspective Against Degradation Mechanisms
Kanchan Cecil,Meena Panchore,Dip Prakash Samajdar 한국전기전자재료학회 2022 Transactions on Electrical and Electronic Material Vol.23 No.5
Heterogeneous gate dielectric (HD) dopingless n-type tunnel-FET (HD-DLTFET) is proposed with improved reliability performance against distinct drain current degradation mechanisms. Using calibrated 2-D TCAD device simulations, a comparative reliability analysis has been performed between proposed HD-DLTFET and conventional DLTFET, which shows only 14.2% drain degradation in HD-DLTFET against 41.9% in conventional DLTFET under hot-carrier stress conditions. On the other hand, simulation results confirmed that the drain current degradation mainly occurred due to the presence of interface-trap and/or oxide charges above the tunneling region, which reduced the tunneling field and tunneling current. Precisely, the interface traps induce the transconductance degradation, while, the oxide charges cause a threshold-voltage shift in conventional DLTFET, whereas, HD-DLTFET show negligible degradation under the influence of both interfacetrap and oxide-charges. Hence, HD-DLTFET accomplishes an impressive I ON / I OFF current ratio of 10 13 and 1.6 × reduced average subthreshold swing as compared to conventional DLTFET.
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Impact of Back Gate Bias on Analog Performance of Dopingless Transistor
Rakesh Kumar,Meena Panchore 한국전기전자재료학회 2023 Transactions on Electrical and Electronic Material Vol.24 No.1
In this brief, the impact of back gate bias (Vgb) , on analog performance of silicon on insulator dopingless transistor (SOIDLT) is investigated. It is observed that SOI-DLTs are more immune to Vgb in contrast to its conventional counterpart SOI junctionless transistor (SOI-JLT). When Vgb is increased from -1.5 V to 1.5 V, the variation in transconductance (gm) and intrinsic gain ( gmrO ) of SOI-JLT is 1.3 and 21.4 times higher than SOI-DLT. The insignifi cant variation is observed in gm and gmrO of SOI-DLT against V gb than SOI-JLT due to the use of lightly doped channel. Further, the device reliability of SOI-DLT against impact ionization is evaluated by measuring the electron concentration and electric field near the drain side. We have found that the SOI-DLT is less sensitive to impact ionization in comparison to conventional SOI-JLT. Hence, the simulation results shown in this paper offer an opportunity for future analog integrated circuits designing with SOI-DLT structure under the influence of Vgb .
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