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HyFAT: Affordable Hybrid Fast Address Translating Device Driver for Multichannel-Based Flash Devices
Mativenga, Ronnie,Kwon, Se Jin,Chung, Tae-Sun IEEE 2019 IEEE transactions on consumer electronics Vol.65 No.2
<P>Artificial intelligence (AI)-based consumer electronic (CE) devices generate massive amounts of accumulated hot data. Persisting this data into such devices’ storage media like the universal flash storage (USF) becomes an issue for flash storage system to manage hot data optimally. Consequently, efforts have been made to support many CE applications and achieve high performance and scalability storage in CE devices. However, it is challenging to find a compatible flash translation layer (FTL) for such flash devices, which can efficiently handle frequent updates imposed by the incoming hot data. Moreover, FTL should be able to handle the hot multimedia data that induces cache-miss penalties which in-turn degrades our flash storage performance. This paper proposes a hybrid flash device for fast address translations called HyFAT which is workload-compatible. HyFAT improves device performance and efficiently manages the combined QuadLevel cell (QLC) for data storage and scalability with SingleLevel cell (SLC) for fast mapping entry storage. The experimental results with realistic workloads show that our approach can improve device performance throughput by 18% on average, compared to traditional DFTL and RFTL.</P>
High-Performance Drain-Offset a-IGZO Thin-Film Transistors
Mativenga, M,Min Hyuk Choi,Dong Han Kang,Jin Jang IEEE 2011 IEEE electron device letters Vol.32 No.5
<P>We report the effect of the drain-offset length on the performance of amorphous-indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs). While the field-effect mobility decreases from ~ 40 to 10 cm<SUP>2</SUP>/V·s by increasing the drain-offset length from 0 to 5 μm, the threshold voltage (V<SUB>th</SUB>) and swing (<I>S</I>) remain relatively independent of the offset length variation. Because of its high mobility even for large (5 μm ) offset lengths, the drain-offset a-IGZO TFT can be used to eliminate the kickback voltage in active-matrix displays.</P>
Mativenga, Mallory,Sungjin An,Suhui Lee,Jaegwang Um,Di Geng,Mruthyunjaya, Ravi K.,Heiler, Gregory N.,Tredwell, Timothy J.,Jin Jang IEEE 2014 IEEE transactions on electron devices Vol.61 No.6
<P>Intrinsic mobility and intrinsic channel resistance (R<SUB>CH</SUB>) of amorphous, In-Ga-Zn-O (a-IGZO) thin-film transistors (TFTs) with varying channel length (L) are investigated using a gated four-probe back-channel-etched TFT design. The intrinsic R<SUB>CH</SUB> is found to decrease from ~500 to ~250 kΩ per unit area by increasing V<SUB>GS</SUB> from 10 to 20 V. The intrinsic mobility is ~17 cm<SUP>2</SUP>/V·s, which is about 20% higher than that derived from the normal two-point probe measurements. Source and drain parasitic resistance (R<SUB>PAR</SUB>) of the a-IGZO TFTs is found to be of the same order of magnitude as the R<SUB>CH</SUB>-which is different from hydrogenated amorphous-silicon (a-Si:H) TFTs, where TFT operation is dominated by R<SUB>PAR</SUB>.</P>
Mativenga, M.,Choi, J.W.,Hur, J.H.,Kim, H.J.,Jang, Jin The Korean Infomation Display Society 2011 Journal of information display Vol.12 No.1
Highly stable amorphous indium.gallium.zinc-oxide (a-IGZO) thin-film transistors (TFTs) were fabricated with an etchstopper and via-hole structure. The TFTs exhibited 40 $cm^2$/V s field-effect mobility and a 0.21 V/dec gate voltage swing. Gate-bias stress induced a negligible threshold voltage shift (${\Delta}V_{th}$) at room temperature. The excellent stability is attribute to the via-hole and etch-stopper structure, in which, the source/drain metal contacts the active a-IGZO layer through two via holes (one on each side), resulting in minimized damage to the a-IGZO layer during the plasma etching of the source/drain metal. The comparison of the effects of the DC and AC stress on the performance of the TFTs at $60^{\circ}C$ showed that there was a smaller ${\Delta}V_{th}$ in the AC stress compared with the DC stress for the same effective stress time, indicating that the trappin of the carriers at the active layer-gate insulator interface was the dominant degradation mechanism.
Mativenga, M.,Di Geng,Chang, J. H.,Tredwell, T. J.,Jin Jang IEEE 2012 IEEE electron device letters Vol.33 No.6
<P>Stable and fast-switching thin-film transistors and circuits incorporating 5-nm-thick amorphous-InGaZnO (a-IGZO) active layers are demonstrated, and their dependence on channel length is studied. Turn-on voltage shifts in the positive gate voltage direction as the channel length increases. A low area density of defects in the bulk a-IGZO, which is ultrathin, results in good stability under positive bias stress, whereas interdiffusion of electrons/electron donors from the highly doped source and drain regions to the channel edges results in the dependence of turn-on voltage on channel length. Stable operation of an 11-stage ring oscillator is achieved with a propagation delay time of ~97 μs/stage due to reduced gate-to-drain overlap capacitance and parasitic resistances.</P>
Mativenga, Mallory,Su Hwa Ha,Di Geng,Dong Han Kang,Mruthyunjaya, Ravi K.,Heiler, Gregory N.,Tredwell, Timothy J.,Jin Jang IEEE 2014 IEEE transactions on electron devices Vol.61 No.9
<P>We report a low-voltage-driven amorphous indium-gallium-zinc oxide (a-IGZO) semiconductor-based Corbino (circular) thin-film transistor (TFT) with infinite output resistance beyond pinchoff. The Corbino TFT has inner and outer concentric ring electrodes, and when the latter is the drain, channel width (W) decreases with channel length (L), such that the W/L ratio is not changed after pinchoff. As demonstrated herein, this a-IGZO Corbino TFT is, therefore, a good candidate for uniform current drivers in applications, such as active-matrix organic light-emitting diode display pixels, where it would maintain the same drive (diode) currents, even with variations in supply voltage (V<SUB>DD</SUB>).</P>
Fully Transparent and Rollable Electronics
Mativenga, Mallory,Geng, Di,Kim, Byungsoon,Jang, Jin American Chemical Society 2015 ACS APPLIED MATERIALS & INTERFACES Vol.7 No.3
<P>Major obstacles toward the manufacture of transparent and flexible display screens include the difficulty of finding transparent and flexible semiconductors and electrodes, temperature restrictions of flexible plastic substrates, and bulging or warping of the flexible electronics during processing. Here we report the fabrication and performance of fully transparent and rollable thin-film transistor (TFT) circuits for display applications. The TFTs employ an amorphous indium–gallium–zinc oxide semiconductor (with optical band gap of 3.1 eV) and amorphous indium–zinc oxide transparent conductive electrodes, and are built on 15-μm-thick solution-processed colorless polyimide (CPI), resulting in optical transmittance >70% in the visible range. As the CPI supports processing temperatures >300 °C, TFT performance on plastic is similar to that on glass, with typical field-effect mobility, turn-on voltage, and subthreshold voltage swing of 12.7 ± 0.5 cm<SUP>2</SUP>/V·s, −1.7 ± 0.2 V, and 160 ± 29 mV/dec, respectively. There is no significant degradation after rolling the TFTs 100 times on a cylinder with a radius of 4 mm or when shift registers, each consisting of 40 TFTs, are operated while bent to a radius of 2 mm. For handling purposes, carrier glass is used during fabrication, together with a very thin (∼1 nm) solution-processed carbon nanotube (CNT)/graphene oxide (GO) backbone that is first spin-coated on the glass to decrease adhesion of the CPI to the glass; peel strength of the CPI from glass decreases from 0.43 to 0.10 N/cm, which eases the process of detachment performed after device fabrication. Given that the CNT/GO remains embedded under the CPI after detachment, it minimizes wrinkling and decreases the substrate’s tensile elongation from 8.0% to 4.6%. Device performance is also stable under electrostatic discharge exposures up to 10 kV, as electrostatic charge can be released via the conducting CNTs.</P><P><B>Graphic Abstract</B> <IMG SRC='http://pubs.acs.org/appl/literatum/publisher/achs/journals/content/aamick/2015/aamick.2015.7.issue-3/am506937s/production/images/medium/am-2014-06937s_0007.gif'></P><P><A href='http://pubs.acs.org/doi/suppl/10.1021/am506937s'>ACS Electronic Supporting Info</A></P>
M. Mativenga,J.W. Choi,J.H. Hur,H.J. Kim,Jin Jang 한국정보디스플레이학회 2011 Journal of information display Vol.12 No.1
Highly stable amorphous indium–gallium–zinc-oxide (a-IGZO) thin-film transistors (TFTs) were fabricated with an etchstopper and via-hole structure. The TFTs exhibited 40 cm2/V s field-effect mobility and a 0.21 V/dec gate voltage swing. Gate-bias stress induced a negligible threshold voltage shift (Vth) at room temperature. The excellent stability is attributed to the via-hole and etch-stopper structure, in which, the source/drain metal contacts the active a-IGZO layer through two via holes (one on each side), resulting in minimized damage to the a-IGZO layer during the plasma etching of the source/drain metal. The comparison of the effects of the DC and AC stress on the performance of the TFTs at 60◦C showed that there was a smaller Vth in the AC stress compared with the DC stress for the same effective stress time, indicating that the trapping of the carriers at the active layer–gate insulator interface was the dominant degradation mechanism.