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반도체 IC 고장분석에 적합한 ESD Stress Mode 선정
박상일(Sang-Il Park),두수연(Su-Yeon Doo),장미순(Mi-soon Chang),장석원(Seog-Weon Chang),곽계달(Kae-Dal Kwack) 대한기계학회 2007 대한기계학회 춘추학술대회 Vol.2007 No.10
Although used for Machine Model(MM) Electrostatic Discharge(ESD) test, JEDEC standard has Integrated Circuit(IC) test for all power pin for a long time. This study selects an effective method for ESD test which is used for only reference. To reach in the planning stage both EEROM IC that has analog circuit and Audio Dac IC that has analog and digital circuit are used. Also three samples are selected for each test to enhance reliability. About the positive and negative ESD stress we have estimated that protection relative to the V<SUB>dd</SUB> is the weakest.