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A 2-40 Gb/s PAM4/NRZ Dual-mode Wireline Transmitter with 4:1 MUX in 65-nm CMOS
Fangxu Lv,Xuqiang Zheng,Feng Zhao,Jianye Wang,Ziqiang Wang,Shuai Yuan,Yajun He,Chun Zhang,Zhihua Wang 대한전자공학회 2018 Journal of semiconductor technology and science Vol.18 No.2
This paper presents a 2-40 Gb/s dual-mode wireline transmitter supporting the four-level pulse amplitude modulation (PAM4) and non-return-tozero (NRZ) modulation with a multiplexer (MUX)-based two-tap feed-forward equalizer (FFE). An edgeacceleration technique is proposed for the 4:1 MUX to increase the bandwidth. By utilizing a dedicated cascode current source, the output swing can achieve 900 mV with a level deviation of only 0.12% for PAM4. Fabricated in a 65-nm CMOS process, the transmitter consumes 117 mW and 89 mW at 40 Gb/s in PAM4 and NRZ at 1.2 V supply.
Jau-Ji Jou,Tien-Tsorng Shih,Chih-Chen Peng,Hao-Wen Hsu,Xuan-Yi Ye 대한전자공학회 2021 Journal of semiconductor technology and science Vol.21 No.5
In this study, an inductorless broadband transimpedance amplifier (TIA) is implemented using TSMC 90-nm complementary metal-oxide-semiconductor (CMOS) technology. A regulated cascode circuit with low input impedance is used as the input stage of the TIA. The core amplifier is a fully differential amplifier with active feedback. The output stage of the TIA is an equalizer based on a differential amplifier with a source degenerated resistor and capacitor. The TIA has a bandwidth of 24.8 GHz and good linearity. In the TIA chip testing, clear 25-Gb/s nonreturn to zero and 50-Gb/s four-level pulse amplitude modulation eye diagrams can be observed.
Adaptive Non-speculative DFE with Extended Time Constraint for PAM-4 Receiver
Do-Hyeon Kwon,Hyung-Wook Lee,Kyeong-Min Ko,Taek-Joon An,Jin-Ku Kang 대한전자공학회 2021 Journal of semiconductor technology and science Vol.21 No.2
This paper presents a novel approach to solve the time constraint issue of DFE with PAM4 signaling. By using track and hold operation to sample signals of the same level at two points, the time constraint of 1 UI in direct DFE can be extended to 1.5UI. The FIR-tap employs LVDS structure to maintain common voltage and SS-LMS algorithm is used to obtain the optimal tap weight. The first post-cursor ISI cancellation is done by the LVDS tap and a sufficient settling time is provided by the proposed DFE. The proposed structure may eliminate the loop unrolling speculative DFE for PAM-4, which leads to less hardware for PAM-4 DFE implementation. A PAM-4 serial link using the proposed DFE was designed in a 65nm CMOS technology and analyzed. Channels with 11.9 dB and 13.8 dB losses were compensated through CTLE and the proposed 1 tap DFE, and simulation results demonstrate the time constraint can be extended without deterioration of the eye opening.