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- 주제어 : Switched-diode topologies (검색결과 2 건)
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A Modified Switched-Diode Topology for Cascaded Multilevel Inverters
Karasani, Raghavendra Reddy,Borghate, Vijay B.,Meshram, Prafullachandra M.,Suryawanshi, H.M. The Korean Institute of Power Electronics 2016 JOURNAL OF POWER ELECTRONICS Vol.16 No.5
In this paper, a single phase modified switched-diode topology for both symmetrical and asymmetrical cascaded multilevel inverters is presented. It consists of a Modified Switched-Diode Unit (MSDU) and a Twin Source Two Switch Unit (TSTSU) to produce distinct positive voltage levels according to the operating modes. An additional H-bridge synthesizes a voltage waveform, where the voltage levels of either polarity have less Total Harmonic Distortion (THD). Higher-level inverters can be built by cascading MSDUs. A comparative analysis is done with other topologies. The proposed topology results in reductions in the number of power switches, losses, installation area, voltage stress and converter cost. The Nearest Level Control (NLC) technique is employed to generate the gating signals for the power switches. To verify the performance of the proposed structure, simulation results are carried out by a PSIM under both steady state and dynamic conditions. Experimental results are presented to validate the simulation results.
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A Modified Switched-Diode Topology for Cascaded Multilevel Inverters
Raghavendra Reddy Karasani,Vijay B. Borghate,Prafullachandra M. Meshram,H. M. Suryawanshi 전력전자학회 2016 JOURNAL OF POWER ELECTRONICS Vol.16 No.5
In this paper, a single phase modified switched-diode topology for both symmetrical and asymmetrical cascaded multilevel inverters is presented. It consists of a Modified Switched-Diode Unit (MSDU) and a Twin Source Two Switch Unit (TSTSU) to produce distinct positive voltage levels according to the operating modes. An additional H-bridge synthesizes a voltage waveform, where the voltage levels of either polarity have less Total Harmonic Distortion (THD). Higher-level inverters can be built by cascading MSDUs. A comparative analysis is done with other topologies. The proposed topology results in reductions in the number of power switches, losses, installation area, voltage stress and converter cost. The Nearest Level Control (NLC) technique is employed to generate the gating signals for the power switches. To verify the performance of the proposed structure, simulation results are carried out by a PSIM under both steady state and dynamic conditions. Experimental results are presented to validate the simulation results.
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