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FPGA Based Low Power DES Algorithm Design and Implementation using HTML Technology
Vandana Thind,Bishwajeet Pandey,Kartik Kalia,D M Akbar Hussain,Teerath Das,Tanesh Kumar 보안공학연구지원센터 2016 International Journal of Software Engineering and Vol.10 No.6
In this particular work, we have done power analysis of DES algorithm implemented on 28nm FPGA using HTML (H-HSUL, T-TTL, M-MOBILE_DDR, L-LVCMOS) technology. In this research, we have used high performance software Xilinx ISE where we have selected four different IO Standards i.e. MOBILE_DDR, HSUL_12, LVTTL and LVCMOS (LVCMOS_15, LVCMOS_18, LVCMOS_25 and LVCMOS_33). We have done power analysis of on-chip power like clock power, signals power, IO power, leakage power and supply power. We notified our analysis at five different voltages like 0.5V, 0.8V, 1.0V, 1.2V and 1.5V.