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LOGIC SYNTHESIS AND SILICON COMPILATION FOR TELECOMMUNICATION SYSTEMS
Rabaey, D. 대한전자공학회 1989 ICVC : International Conference on VLSI and CAD Vol.1 No.1
This paper makes a discussion on the application of silicon compilation techniques for the implementation of telecommunication systems. This approach is illustrated with the speech decoder for the Pan European Mobile Radio System, which was designed with the Cathedral II DSP silicon compiler. A comparison between this implementation and a general DSP processor implementation is made.
Exploring the Architecture and Algorithmic Space for Signal Processing Applications
Rabaey, Jan M.,Guerra, Lisa M. 대한전자공학회 1993 ICVC : International Conference on VLSI and CAD Vol.3 No.1
The basic ingredients for a comprehensive exploration of the design space are presented: algorithmic and architecture selection and transformations. Failure to explore any one of these domains can severely limit the quality of the generated design. Techniques for exploration are described, with emphasis on custom ASIC implementations as generated by the HYPER framework. The effect necessary to perform a comprehensive search using contemporary tools is unreasonably large. This is even more tree when multiple hardware platforms (including, for instance, programmable processors) are considered. A means of performing a fast scan of the design space and providing guidance to the search based on performance estimation is proposed. The framework, called HYPERSPACE, is founded upon a set of structural properties of computational algorithms.