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A 4Gb/s CMOS Multiplexer Circuit
Parng,Tai Ming,Liu,Wen Tai,Chu,Hung Chi 대한전자공학회 1997 ICVC : International Conference on VLSI and CAD Vol.5 No.1
Based on a special multiplexing technique and delay locked loop, a high-speed CMOS multiplexer circuit is proposed for increasing the output data bit rate of CMOS multiplexers. Its data bit rate can be several times higher than the maximum clock frequency (FQx} imposed by the intrinsic speed performance of CMOS circuits. A 4-to-1 multiplexer, implemented in a 0.8 ㎛ CMOS process technology, has been designed based on the proposed circuit scheme. Spice simulation results show that the circuit, running at F_(max) = 1 GHz, can achieve a maximum output data bit rate of 4 Gb/s.
Design Formalism for Lookahead Circuits
Shyur, Jui Ching,Chen, Hung Pin,Parng, Tai Ming 대한전자공학회 1993 ICVC : International Conference on VLSI and CAD Vol.3 No.1
We present a formal method that helps transform iterative arrays into parallel lookahead implementations. By using proposed augmented Boolean vectors and matrices, together with a proposed algorithm to eliminate non-linear mapping of recurrence relations of an iterative array, a linear mapping and its corresponding prefix problem can be formulated. As this prefix problem can be parallelly solved, lookahead implementations can then be designed.