A pulse-frequency modulation sensor using memristive-based inhibitory interconnections.

Kavehei, Omid,Lee, Sang-Jin,Cho, Kyoung-Rok,Al-Sarawi, Said,Abbott, Derek American Scientific Publishers 2013 Journal of Nanoscience and Nanotechnology Vol.13 No.5

<P>This paper proposes a programmable inhibitory interconnection network between pixels in an array of novel low-voltage Schmitt-trigger-based PFM sensors that will be of interest for future applications in memristor-based early vision processing. In addition, a new low-power inverter-based pulse-frequency modulation (PFM) design and its integration with the network is also presented. To ensure no change in the memristors conductance in the network, the CMOS imager was designed for low voltage operation. That has resulted in a significant power reduction, better than 60%, and a comparable linear dynamic range when compared to published designs in the literature. The design was performed using a 0.13 um Samsung Electronics standard CMOS process, using 0.75 V supply voltage.</P>

The fourth element: characteristics, modelling and electromagnetic theory of the memristor

Kavehei, O.,Iqbal, A.,Kim, Y. S.,Eshraghian, K.,Al-Sarawi, S. F.,Abbott, D. The Royal Society 2010 Proceedings, Mathematical, physical, and engineeri Vol.466 No.2120

<P> In 2008, researchers at the Hewlett-Packard (HP) laboratories published a paper in <I>Nature</I> reporting the development of a new basic circuit element that completes the missing link between charge and flux linkage, which was postulated by Chua in 1971 (Chua 1971 <I>IEEE Trans. Circuit Theory</I>18 , 507-519 ( doi:10.1109/TCT.1971.1083337 )). The HP memristor is based on a nanometre scale TiO 2 thin film, containing a- doped region and an undoped region. Further to proposed applications of memristors in artificial biological systems and non-volatile RAM, they also enable reconfigurable nanoelectronics. Moreover, memristors provide new paradigms in application-specific integrated circuits and field programmable gate arrays. A significant reduction in area with an unprecedented memory capacity and device density are the potential advantages of memristors for integrated circuits. This work reviews the memristor and provides mathematical and SPICE models for memristors. Insight into the memristor device is given via recalling the quasi-static expansion of Maxwell’s equations. We also review Chua’s arguments based on electromagnetic theory. </P>

Integrated memristor-MOS (M2) sensor for basic pattern matching applications.

Kavehei, Omid,Cho, Kyoung-Rok,Lee, Sang-Jin,Al-Sarawi, Said,Eshraghian, Kamran,Abbott, Derek American Scientific Publishers 2013 Journal of Nanoscience and Nanotechnology Vol.13 No.5

<P>This paper introduces an integrated sensor circuit based on an analog Memristor-MOS (M2) pattern matching building block that calculates the similarity/dissimilarity between two analog values. A new approach for a pulse-width modulation pixel image sensor compatible with the memristive-MOS matching structure is introduced allowing direct comparison between incoming and stored images. The pulsed-width encoded information from the pixels is forwarded to a matching circuitry that provides an anti-Gaussian-like comparison between the states of memristors. The non-volatile and multi-state memory characteristics of memristor, together with the related ability to be programmed at any one of the intermediate states between logic '1' and logic '0' brings us closer to the implementation of bio-machines that can eventually emulate human-like sensory functions.</P>

An Analytical Approach for Memristive Nanoarchitectures

Kavehei, O.,Al-Sarawi, S.,Kyoung-Rok Cho,Eshraghian, K.,Abbott, D. IEEE 2012 IEEE TRANSACTIONS ON NANOTECHNOLOGY Vol.11 No.2

<P>As conventional memory technologies are challenged by their technological physical limits, emerging technologies driven by novel materials are becoming an attractive option for future memory architectures. Among these technologies, Resistive Memories (ReRAM) created new possibilities because of their nanofeatures and unique <I>I</I>-<I>V</I> characteristics. One particular problem that limits the maximum array size is interference from neighboring cells due to sneak-path currents. A possible device level solution to address this issue is to implement a memory array using complementary resistive switches (CRS). Although the storage mechanism for a CRS is fundamentally different from what has been reported for memristors (low and high resistances), a CRS is simply formed by two series bipolar memristors with opposing polarities. In this paper, our intention is to introduce modeling principles that have been previously verified through measurements and extend the simulation principles based on memristors to CRS devices and, hence, provide an analytical approach to the design of a CRS array. The presented approach creates the necessary design methodology platform that will assist designers in implementation of CRS devices in future systems.</P>

Memristive Device Fundamentals and Modeling: Applications to Circuits and Systems Simulation

Eshraghian, K.,Kavehei, O.,Kyoung-Rok Cho,Chappell, J. M.,Iqbal, A.,Al-Sarawi, S. F.,Abbott, D. IEEE 2012 Proceedings of the Institute of Electrical and Ele Vol.100 No.6

<P>The nonvolatile memory property of a memristor enables the realization of new methods for a variety of computational engines ranging from innovative memristive-based neuromorphic circuitry through to advanced memory applications. The nanometer-scale feature of the device creates a new opportunity for realization of innovative circuits that in some cases are not possible or have inefficient realization in the present and established design domain. The nature of the boundary, the complexity of the ionic transport and tunneling mechanism, and the nanoscale feature of the memristor introduces challenges in modeling, characterization, and simulation of future circuits and systems. Here, a deeper insight is gained in understanding the device operation, leading to the development of practical models that can be implemented in current computer-aided design (CAD) tools.</P>

Multiprotocol-induced plasticity in artificial synapses

Kornijcuk, Vladimir,Kavehei, Omid,Lim, Hyungkwang,Seok, Jun Yeong,Kim, Seong Keun,Kim, Inho,Lee, Wook-Seong,Choi, Byung Joon,Jeong, Doo Seok The Royal Society of Chemistry 2014 Nanoscale Vol.6 No.24

<P>We suggest a ‘universal’ electrical circuit for the realization of an artificial synapse that exhibits long-term plasticity induced by different protocols. The long-term plasticity of the artificial synapse is basically attributed to the nonvolatile resistance change of the bipolar resistive switch in the circuit. The synaptic behaviour realized by the circuit is termed ‘universal’ inasmuch as (i) the shape of the action potential is not required to vary so as to implement different plasticity-induction behaviours, activity-dependent plasticity (ADP) and spike-timing-dependent plasticity (STDP), (ii) the behaviours satisfy several essential features of a biological chemical synapse including firing-rate and spike-timing encoding and unidirectional synaptic transmission, and (iii) both excitatory and inhibitory synapses can be realized using the same circuit but different diode polarity in the circuit. The feasibility of the suggested circuit as an artificial synapse is demonstrated by conducting circuit calculations and the calculation results are introduced in comparison with biological chemical synapses.</P>

3-D System-on-System (SoS) Biomedical-Imaging Architecture for Health-Care Applications

Sang-Jin Lee,Kavehei, O,Yoon-Ki Hong,Tae Won Cho,Younggap You,Kyoungrok Cho,Eshraghian, K IEEE 2010 IEEE transactions on biomedical circuits and syste Vol.4 No.6

<P>This paper presents the implementation of a 3-D architecture for a biomedical-imaging system based on a multilayered system-on-system structure. The architecture consists of a complementary metal-oxide semiconductor image sensor layer, memory, 3-D discrete wavelet transform (3D-DWT), 3-D Advanced Encryption Standard (3D-AES), and an RF transmitter as an add-on layer. Multilayer silicon (Si) stacking permits fabrication and optimization of individual layers by different processing technology to achieve optimal performance. Utilization of through silicon via scheme can address required low-power operation as well as high-speed performance. Potential benefits of 3-D vertical integration include an improved form factor as well as a reduction in the total wiring length, multifunctionality, power efficiency, and flexible heterogeneous integration. The proposed imaging architecture was simulated by using Cadence Spectre and Synopsys HSPICE while implementation was carried out by Cadence Virtuoso and Mentor Graphic Calibre.</P>

High Fill Factor Low-Voltage CMOS Image Sensor Based on Time-to-Threshold PWM VLSI Architecture

Kyoungrok Cho,Sang-Jin Lee,Kavehei, Omid,Eshraghian, Kamran IEEE 2014 IEEE transactions on very large scale integration Vol.22 No.7

<P>This paper presents a CMOS image sensor (CIS) VLSI architecture based on a single-inverter time-to-threshold pulsewidth modulation circuitry capable of operating as low as 330-mV supply voltage while retaining a signal-to-noise ratio of 24 dB; an important characteristic being demanded by very low voltage portable CIS-based equipment such as disposable medical cameras and on-chip autonomous wireless security vision systems. A 64 × 64 pixel array was fabricated using standard 130-nm CMOS process consuming only 5.9 nW/pixel with integration time of 2 ms at +0.5 V supply. The high fill factor of 58% facilitated a better SNR at a low supply voltage when compared with other CIS architectures. The pixel has a dynamic range of 54 dB with 7.8 frame per second.</P>

Probability Analysis of Double Layer Barrel Vaults Considering the Effect of Initial Curvature and Length Imperfections Simultaneously

M. Tahamouli Roudsari,M. Gordini,H. Fazeli,B. Kavehei 한국강구조학회 2017 International Journal of Steel Structures Vol.17 No.3

Load carrying capacity of reticulated space structures majorly depend on the structures’ imperfections. Imperfections in initial curvature, length, and residual stress of members are all innately random and can affect the load-bearing capacity of the members and consequently that of the structure. The present study investigated the effect of the probability distribution of initial curvature imperfection and lack of fit of members on the load-bearing capacity of double-layer barrel vault space structures with different types of support. A random number was first assigned to each member using gamma and normal distributions for initial curvature and member length imperfections, respectively. Afterwards, the ultimate bearing capacity and the collapse behavior of the structure was determined using nonlinear finite-element analysis in OpenSees software and finally structures reliability was acquired. The results demonstrate that the collapse behavior of doable-layer barrel vault space structures is sensitive to the random distribution of initial imperfections.