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Heterogenous Gate Dielectric DLTFET: Reliability Perspective Against Degradation Mechanisms
Kanchan Cecil,Meena Panchore,Dip Prakash Samajdar 한국전기전자재료학회 2022 Transactions on Electrical and Electronic Material Vol.23 No.5
Heterogeneous gate dielectric (HD) dopingless n-type tunnel-FET (HD-DLTFET) is proposed with improved reliability performance against distinct drain current degradation mechanisms. Using calibrated 2-D TCAD device simulations, a comparative reliability analysis has been performed between proposed HD-DLTFET and conventional DLTFET, which shows only 14.2% drain degradation in HD-DLTFET against 41.9% in conventional DLTFET under hot-carrier stress conditions. On the other hand, simulation results confirmed that the drain current degradation mainly occurred due to the presence of interface-trap and/or oxide charges above the tunneling region, which reduced the tunneling field and tunneling current. Precisely, the interface traps induce the transconductance degradation, while, the oxide charges cause a threshold-voltage shift in conventional DLTFET, whereas, HD-DLTFET show negligible degradation under the influence of both interfacetrap and oxide-charges. Hence, HD-DLTFET accomplishes an impressive I ON / I OFF current ratio of 10 13 and 1.6 × reduced average subthreshold swing as compared to conventional DLTFET.