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Rasi Prasetio,Yunus Daud,Johanes Hutabarat,Hendarmawan Hendarmawan 한국지질과학협의회 2021 Geosciences Journal Vol.25 No.4
Wayang Windu geothermal field, which is situated in quaternary volcanic rock, has been delivering 227 MW of electricity and is planned to be developed in near future. Isotope and geochemistry study has been done to support understanding of the system. Samples were taken from thermal manifestations and production wells (two-phase and dry steam wells) to analyse its isotope and chemical compositions. Most of the hot springs are bicarbonate type and have neutral pH values, except for steam heated waters found near fumarolic fields, which are acid sulfate type waters. Deep brine fluids are of mature chloride type, while other deep dilute fluids are bicarbonate type indicates the existance of condensate layer. Solute and gas geothermometer calculation showed good agreement with measured temperature, i.e., 280–300 °C. However, gas-gas equilibria calculation showed increasing T and decreasing y (steam fraction) compare to previous study which indicates contribution form hotter source with high liquid saturation. Aside from different recharge area of thermal manifestation and production wells, the isotopes composition also shows physical processes in reservoir, i.e., adiabatic boiling, steam separation at different temperature (140–260 °C) and steam fraction (0.30–0.65), and also mixing process with meteoric water.
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Low-cost Hardware that Accelerates Frequent Item Counting with an FPGA
Mpho Gift Doctor Gololo,Hendarmawan,Qian Zhao,Motoki Amagasaki,Masahiro Iida,Morihiro Kuga,Toshinori Sueyoshi 대한전자공학회 2017 IEIE Transactions on Smart Processing & Computing Vol.6 No.5
In this paper, hardware acceleration using a field programmable gate array is proposed to provide low development–cost and high-performance stream processing hardware. This research is proposed as an enhancement to the software-based application for frequent item counting (FIC) and to contribute to hardware-based FIC for hardware/software co-design. We design an experiment by taking advantage of high-level synthesis (HLS) and the heterogeneous Computing Oriented Development Environment (hCODE), an open source platform providing a methodology and a tool for scalable and portable Internet Protocol design. The proposed scheme considers optimization techniques offered by HLS compilers, such as the pipeline technique, loop unrolling, and memory partition. Our implementation shows that the proposed scheme achieves a better overall performance than a software scheme, and more importantly, introduces fast and low development costs for hardware accelerators.
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