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Study on Impact-Ionization MOS for 1T-DRAM Operation
Jangho Jung(정장호),Hamin Park(박하민) 대한전자공학회 2023 대한전자공학회 학술대회 Vol.2023 No.11
In this paper, we implemented and analyzed the impact-ionization MOS (I-MOS) for 1T-DRAM using TCAD simulation. Based on a TCAD model with reliability ensured through calibration, we demonstrated the feasibility of 1T-DRAM operation through I-MOS parameter optimization and additional Boron doping in the channel region to induce the hysteresis. Furthermore, we analyzed the drain current variation and memory window through a region-specific impact ionization and charge transport analysis of the I-MOS device.
Sang-Il Pyeon(편상일),Seong-Min Park(박성민),Dae-Ung Jeong(정대웅),Hui-Seong Ok(옥희성),Hamin Park(박하민) 대한전자공학회 2023 대한전자공학회 학술대회 Vol.2023 No.11
Following developments in the display industry, research and development related to the application of a-IGZO material are also taking place in the memory field. In this paper, we analyzed the threshold voltage reliability and hump effect of a-IGZO devices under voltage and illumination stress. We comprehensively analyzed the changes in the threshold voltage and the magnitude of the hump effect over time under the situation where negative voltage stress is applied while light stress is intermittently present, and we investigate an oxygen vacancy mechanism to explain the behavior.
Gate-All-Around FET Inner Spacer 두께에 따른 Parasitic Capacitance 모델링
강지훈(Jihun Kang),김현곤(Hyeongon Kim),박하민(Hamin Park) 대한전자공학회 2023 대한전자공학회 학술대회 Vol.2023 No.11
According to the scaling of transistors, the impact of parasitic capacitance is continuously increasing. In the case of gate-all-around FET (GAAFET), various parasitic capacitance elements exist due to its complex three-dimensional structure. In this paper, we conducted modeling of extension capacitance (Cext) in GAAFET based on different inner spacer thickness (TIS). We extracted Cext of GAAFET using TCAD simulation and carried out Cext modeling using elliptical coordinates to the Cartesian system. To establish the model, we divided the distribution of electric fields composing Cext into three regions and ensured consistency between the models of changes in these three regions with TIS and TCAD simulation results. Finally, we analyzed the trend of C<SUB>ext</SUB> changes based on the TIS using the model.
Punch-Through Path 제어 기반의 1T-DRAM 소자
조승준(Seung-Jun Cho),이도현(Do-Hyun Lee),박하민(Hamin Park) 대한전자공학회 2023 대한전자공학회 학술대회 Vol.2023 No.11
As the integration density of conventional 1T-1C DRAM has reached its limits, a new 1T-DRAM structure for higher integration density has been proposed. In this paper, we propose a new 1TDRAM device structure based on the punch-through path control utilizing band-to-band tunneling, and validate the DRAM operation of this structure through TCAD simulation.