Subthreshold Swing Including Tunneling of Sub-20 ㎚ Asymmetric Double Gate MOSFET

Hakkee Jung,Sima Dimitrijev 한국정보통신학회 2016 2016 INTERNATIONAL CONFERENCE Vol.8 No.1

This paper analyzes the subthreshold swing in asymmetric double gate MOSFETs with sub-20 ㎚ channel lengths. The degradation of subthreshold swing due to tunneling effects is investigated using analytical potential distribution and Wentzel–Kramers–Brillouin (WKB) approximation in this paper. This analytical approach is verified by two dimensional simulation. It is shown that the degradation of subthreshold swing increases with both reduction of channel length and increase of channel thickness.

Top and Bottom Gate Voltage Dependent Tunneling Current of Asymmetric DGMOSFET

Hakkee Jung,Ohshin Kwon 한국정보통신학회 2015 2016 INTERNATIONAL CONFERENCE Vol.7 No.1

This paper analyzes the deviation of tunneling current for the change of top and bottom gate voltage of asymmetric double gate(DG) MOSFET. The factors to be able to control the short channel effects are increased since the asymmetric DGMOSFET can be biased differently to top and bottom gate. The condition the ratio of tunneling current in the total off current reduced is obtained for top and bottom gate voltage. The analytical potential model of series form derived from Poisson’s equation and WKB(Wentzel-Kramers-Brillouin) approximation are used to calculate the total off current consisted of the thermionic and tunneling current. As a results, the ratio of tunneling current is significantly decreased with the increase of channel length and thickness in the region of sub-10 nm channel length and thickness. Especially it showed the influence of top and bottom gate voltage for the ratio of tunneling current is vice versa.

Analysis of Oxide Thickness Dependent Threshold Voltage of Asymmetric DGMOSFET

Hakkee Jung 한국정보통신학회 2014 2016 INTERNATIONAL CONFERENCE Vol.6 No.1

The threshold voltage of asymmetric double gate(DG) MOSFET has been analyzed for top and bottom gate oxide thickness using Gaussian doping profiles in channel. The asymmetric DGMOSFET is four terminal device to be able to bias different top and bottom gate voltage respectively. The threshold voltage is defined as the top gate voltage when drain current is 10<SUP>-7</SUP> A per unit channel width in the subthreshold region, given the constant bottom gate voltage. The threshold voltage for asymmetric DGMOSFET has been investigated, using our threshold voltage model for the change of top and bottom gate thickness. As a result, we know the threshold voltage has greatly changed for top and bottom gate oxide thickness, and the changing trend has been influenced on channel length and thickness.

Analysis of Drain Induced Barrier Lowering for Bottom Gate Voltage of Asymmetric DGMOSFET

Hakkee Jung,Dongsoo Jeong 한국정보통신학회 2015 2016 INTERNATIONAL CONFERENCE Vol.7 No.1

This paper analyzes the drain induced barrier lowering (DIBL) for the bottom gate voltage of asymmetric double gate(DG) MOSFET. The possibility to be able to control DIBL by the bottom gate voltage is observed in this paper. The analytical potential model of series form derived from Poisson’s equation using Gaussian distribution is used to solve the off current. The DIBL is investigated for bottom gate voltage with parameters of channel length, and projected range and standard projected deviation. As a result, the DIBL is significantly increased with the decrease of channel length.

Analysis of Channel Dimension Dependent Threshold Voltage for Asymmetric DGMOSFET

Hakkee Jung,Ohshin Kwon 한국정보통신학회 2014 2016 INTERNATIONAL CONFERENCE Vol.6 No.1

The threshold voltage roll-off of asymmetric double gate(DG) MOSFET has been analyzed for channel length and channel thickness using Gaussian doping profiles in channel. This threshold voltage roll-off is serious short channel effects like subthreshold swing degradation and drain induced barrier lowering. The asymmetric DGMOSFET to be able to make with different top and bottom gate oxide thickness can control threshold voltage by adjusting the top and bottom gate oxide thickness as well as channel length and thickness. The threshold voltage roll-off is investigated for dimension of asymmetric DGMOSFET in this study. As a result to observe threshold voltage with a parameter of top and bottom gate oxide thickness, we know the movement of threshold voltage has greatly occurred in the short channel length and thin channel thickness, and changing pattern of threshold voltage for channel length and thickness has been influenced by top and bottom gate oxide thickness.

Conduction Path Dependent Subthreshold Swing of Asymmetric Double Gate MOSFET

Hakkee Jung,Jongin Lee,Dongsoo Jeong 한국정보통신학회 2014 2016 INTERNATIONAL CONFERENCE Vol.6 No.1

The subthreshold swing and conduction path of asymmetric double gate(DG) MOSFET has been analyzed for channel thickness with a parameter of oxide thickness using Gaussian doping profiles in channel. The two dimensional analytical potential profile model of asymmetric DGMOSFET based on a summation of series has been used to derive the analytical subthreshold swing model. As a result to observe the relation of subthreshold swing and conduction path using this model, subthreshold swing depends on conduction path to change for top and bottom gate oxide thickness with channel length and thickness. We know the conduction path moves into gate contact biased with higher voltage, and subthreshold swing is greatly increased with movement of conduction path into bottom gate contact in the case of higher bottom gate voltage.

Analysis of DIBL for DGMOSFET Using Structure and Process Parameters

Hakkee Jung,Jihyeong Han,Jongin Lee,Sima Dimitrijev 한국정보통신학회 2011 2016 INTERNATIONAL CONFERENCE Vol.4 No.1

Analysis of Tunneling Current for Gate Oxide Thickness of Sub-10 nm Asymmetric Double Gate MOSFET

Hakkee Jung 한국정보통신학회 2015 2016 INTERNATIONAL CONFERENCE Vol.7 No.1

This paper analyzes the deviation of tunneling current for the change of top and bottom gate oxide thickness of sub-10 nm asymmetric double gate MOSFET. The influence of tunneling current is investigated in this study as the portion of tunneling current for off current was calculated for the change of top and bottom gate oxide thickness. The tunneling current is obtained by the WKB(Wentzel-Kramers-Brillouin) approximation and analytical potential distribution derived from Poisson equation. As a results, the tunneling current is significantly influenced by gate oxide thickness in asymmetric DGMOSFET with the channel length under 10 nm. Especially it showed the great deviation with parameters of top and bottom gate voltage.

Analysis of Flat-Band-Voltage Dependent Breakdown Voltage for 10 nm Double Gate MOSFET

Jung, Hakkee,Dimitrijev, Sima The Korea Institute of Information and Commucation 2018 Journal of information and communication convergen Vol.16 No.1

The existing modeling of avalanche dominated breakdown in double gate MOSFETs (DGMOSFETs) is not relevant for 10 nm gate lengths, because the avalanche mechanism does not occur when the channel length approaches the carrier scattering length. This paper focuses on the punch through mechanism to analyze the breakdown characteristics in 10 nm DGMOSFETs. The analysis is based on an analytical model for the thermionic-emission and tunneling currents, which is based on two-dimensional distributions of the electric potential, obtained from the Poisson equation, and the Wentzel-Kramers-Brillouin (WKB) approximation for the tunneling probability. The analysis shows that corresponding flat-band-voltage for fixed threshold voltage has a significant impact on the breakdown voltage. To investigate ambiguousness of number of dopants in channel, we compared breakdown voltages of high doping and undoped DGMOSFET and show undoped DGMOSFET is more realistic due to simple flat-band-voltage shift. Given that the flat-band-voltage is a process dependent parameter, the new model can be used to quantify the impact of process-parameter fluctuations on the breakdown voltage.

Analysis of Flat Band Voltage Dependent Breakdown Voltage for Sub-10 nm DGMOSFET

Hakkee Jung,Ohshin Kwon 한국정보통신학회 2017 2016 INTERNATIONAL CONFERENCE Vol.9 No.1

A model for the flat band voltage dependent breakdown voltage of sub-10 nm doublegate MOSFETs (DGMOSFETs) is proposed in this paper. Flat band voltage of gates is process dependent parameter by unintended process variables and uncertainties. Since variation of flat band voltage significantly effects on current-voltage characteristics, breakdown voltage depends on flat band voltage. Since avalanche is not occurred in sub- 10 nm DGMOSFETs, breakdown by punch-through effect arises from lowering of potential energy emerges even in the region of low drain voltage. The drain breakdown voltage becomes very small with dramatic down scaling due to abrupt increasing of tunneling current. The new model is used to investigate the flat band voltage dependent breakdown voltage with parameters of channel dimension and top/bottom oxide thickness of sub-10 nm DGMOSFET. The breakdown voltage is decreased with reduction of channel length and flat band voltage and increase of channel thickness. The breakdown voltage is varied for top/bottom gate oxide thicknesses.