http://chineseinput.net/에서 pinyin(병음)방식으로 중국어를 변환할 수 있습니다.
변환된 중국어를 복사하여 사용하시면 됩니다.
A New CAD Environment for Benchmarks of Analog Circuit Sizing Tools and Algorithms
Marin,David,Escudero,Juan,Oliver,Joan,Flandre,Denis 대한전자공학회 1997 ICVC : International Conference on VLSI and CAD Vol.5 No.1
This paper presents a new open environment for the design of analog circuits exchanging information from existing tools. The main features of these tools have been extended in CONNAN by means of a netlist analyzer, the interaction with a commercial CAD tool and a transistor model manager that solves some common problems of sizing tools based on electrical simulators. As an initial test CONNAN is applied to the sizing of analog IC based on electrical simulators and simulated annealing algorithms.
Abnormal drain current (ADC) effect and its mechanism in FD SOI MOSFETs
Yun, J.-G.,Cristoloveanu, S.,Bawedin, M.,Flandre, D.,Lee, Hi-Deok IEEE 2006 IEEE electron device letters Vol.27 No.2
A new type of abnormal drain current (ADC) effect in fully depleted (FD) silicon-on-insulator (SOI) MOSFETs is reported. It is found that the drain current becomes abnormally large for specific front- and back-gate voltages. The drain current exhibits a transient effect due to the floating body behavior and no longer follows the conventional interface coupling theory for these specific front- and back-gate bias conditions. It is shown that the ADC can be generated by the combination of gate-induced drain leakage, transient effects, and parasitic bipolar transistor action in FD SOI MOSFETs.