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Different behaviors of half-metallic ferromagnetism of Cr-doped AlN and InN
Kang, ByungSub,Lee, HaengKi,Kim, KyeongSup,Kang, HeeJae Royal Swedish Academy of Sciences 2009 Physica scripta Vol.79 No.2
<P>The electronic structure and magnetism are studied for the zinc-blende and wurtzite (Al,Cr)N, (Ga,Cr)N and (In,Cr)N by using the full potential linear muffin-tin orbital method. The energy gap (quasi-gap) in Cr-doped wurtzite InN decreases exponentially with increasing the Cr concentration from 0.027 to 0.166. The half-metallicity is retained in the whole range of concentrations considered, whereas for (Al,Cr)N, the half-metallic character disappears at a concentration of 0.166. The Cr magnetic moment in AlN is about 2.12–2.40μ<SUB>B</SUB> Cr atom<SUP>−1</SUP> with changing the Cr concentration, and for Cr in InN, it is a nearly constant value of 3.0 μ<SUB>B</SUB> Cr atom<SUP>−1</SUP>.</P>
강석구,전제호,야마구치 도쿠타로,홍융기,고병섭 성균관대학교 기초과학연구소 1994 論文集 Vol.45 No.2
지질 가수 분해 효소인 리파아제를 이용하여 완충 용액하에서 (±)-2-Hydroxymethyl-3,4-dihydro-2H-pyran의 비대칭 가수 분해 및 여러 가지 유기 용매하에서 (±)-2-acetoxymethyl-3,4-dihydro-2H-pyran의 에스테르화 반응을 하여 화학적으로 유용한 synthon을 얻는 연구를 하였다. Porcine pancreas lipase(PPL)-catalyzed acetylation of (±)-2-thdroxymethyl-3,4-dihydro-2H-pyran with vinyl acetate in organic solvent afforded (S)-(+)-2-acetoxymethyl-3,4-dihydro-2H-pyran. Alternatively, (±)-2-acetoxymethyl-3,4-dihydro-2H-pyran was resolved via PPL catalyzed hydrolysis in acetone-phosphate buffer system to afford (S)-(+)-2-hydroxymethyl-3,4-dihydro-2H-pyran with high enantioselectivity.
Kim, Kwangmin,Kang, Seokjoon,Sim, Jae-Yoon,Park, Hong-June,Kim, Byungsub IEEE 2018 IEEE transactions on very large scale integration Vol.26 No.12
<P>In this paper, we propose a search algorithm to find the worst operation scenario of a cross-point array of a phase-change random access memory to enable a precise read margin evaluation. The search algorithm utilizes a particle swarm optimization method to find the worst scenario quickly and efficiently. In an experiment, the proposed algorithm improves the search speed by <TEX>$39.3\times $</TEX> compared with the previous algorithm. With the improved search speed, the proposed algorithm could find the worst operation scenarios of large arrays whose worst operation scenarios had been only guessed before. In the experiment with a large array, the proposed algorithm proved that the worst high-resistance state read current can be <TEX>$36\times $</TEX> larger than the previous best guess. In the reliability test, the evaluation error of the worst read current found by the proposed algorithm is less than 0.2% with 99% probability. These results show that the proposed search algorithm can improve the precision and efficiency of the read margin evaluation in designing a cross-point phase-change memory array.</P>
Soo-Min Lee,Il-Min Yi,Hae-Kang Jung,Hyunbae Lee,Yong-Ju Kim,Yun-Saing Kim,Byungsub Kim,Jae-Yoon Sim,Hong-June Park IEEE 2014 IEEE journal of solid-state circuits Vol.49 No.11
<P>A low-energy single-ended duobinary transceiver is proposed for the point-to-point DRAM interface with an energy efficiency of 0.56 pJ/bit at 7 Gb/s. The transmitter power is reduced by decreasing the signal swing of transmission channel to 80 mV and replacing the multiplexer and the binary output driver in the transmitter by a duobinary output driver. A trans-impedance amplifier (TIA) is used at the receiver end of transmission channel. The TIA works as a receiver termination and also amplifies the input signal for subsequent processing. Analysis of the feedback loop delay and the nonlinearity of the TIA shows that they do not impose serious problems. The TIA output signal is applied to a duobinary-to-NRZ converter, which is implemented by using a direct feedback 1-tap DFE circuit with a tap-coefficient of 1.0. The reference voltage of the duobinary-to-NRZ converter is calibrated automatically to enable a small-swing signaling. The proposed transceiver chip in a 65 nm CMOS process works at 4.5 Gb/s with a 3' FR4 microstrip line, and at 7 Gb/s with a 0.6' FR4.</P>
Lee, Soo-Min,Lim, Ji-Hoon,Yi, Il-Min,Jang, Young-Jae,Jung, Hae-Kang,Kim, Kyunghoon,Kwon, Daehan,Kim, Byungsub,Sim, Jae-Yoon,Park, Hong-June IEEE 2016 IEEE journal of solid-state circuits Vol.51 No.8
<P>A four-bit four-wire four-level (4B4W4L) single-ended parallel transceiver for the point-to-point DRAM interface achieved a peak reduction of similar to 10 dB in the electromagnetic interference (EMI) H-field power, compared to a conventional 4-bit parallel binary transceiver with the same output driver power of transmitter (TX) and the same input voltage margin of receiver (RX). A four-level balanced coding is used in this work to minimize the simultaneous switching noise at TX, to utilize a differential sensing without a reference voltage at RX, to maintain the pin efficiency of 100%, and also to reduce EMI by setting the sum of currents through the four wires to be zero. A capacitive pre-emphasis scheme modified for four-level signaling is also used at TX to compensate for inter-symbol interference. The transmitted four-level signals are recovered by six differential comparators with an offset compensation and a decoder at RX. The proposed transceiver chip fabricated in a 65 nm CMOS process consumes 2.39 pJ/bit with a 1.2 V supply and a 2 inch FR4 channel at 8 Gb/s.</P>