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Remote carrier trapping in FinFETs with ONO buried layer: Temperature effects
Chang, S.J.,Bawedin, M.,Xiong, W.,Lee, J.H.,Lee, J.H.,Cristoloveanu, S. Pergamon Press 2013 Microelectronics and reliability Vol.53 No.3
The charge trapping mechanisms are studied at room and high temperature in advanced SOI FinFETs fabricated on SiO<SUB>2</SUB>-Si<SUB>3</SUB>N<SUB>4</SUB>-SiO<SUB>2</SUB> (ONO) multi-layer buried insulator (BOX). By applying appropriate back-gate and/or drain bias, the buried nitride layer can trap charges. The coupling mechanism between front and back interfaces enables the front-channel drain current to reflect the presence or absence of trapped/injected charges in the BOX. In this work, the charge trapping/detrapping is induced by a constant drain or back-gate bias or during the scanning of the back-gate voltage. According to the polarity of the trapped charges and their location along the channel, various current levels are observed leading to a memory effect. In order to clarify the charge trapping and coupling mechanisms, the temperature of operation was used as additional experimental parameter. The amount of trapped charges depends not only on the bias conditions but also on temperature and fin geometry. We discuss the 3D coupling effects between the channel and the remote trapped charges.
Xu, Yue,Cristoloveanu, Sorin,Bawedin, Maryline,Im, Ki-Sik,Lee, Jung-Hee Institute of Electrical and Electronics Engineers 2018 IEEE transactions on electron devices Vol. No.
<P>This paper presents a new concept, supported by 3-D TCAD simulations, for improving the performance and subthreshold swing (SS) of enhancement-mode AlGaN/GaN fin-shaped field-effect transistors (FinFETs). By choosing appropriate device parameters, the formation of 2-D electron gas (2DEG) can be delayed such as to ensure simultaneous activation of 2DEG and sidewall MOS channels at positive threshold voltage for normally off operation. The 2DEG channel starts forming in the middle of the fin, whereas the edges are depleted by the lateral MOS gates. Not only increasing the gate voltage does the 2DEG charge increase, but also the effective width is enlarged being less depleted by the gates. This double-2DEG mechanism adds to the regular MOS channels on the sidewalls and enables enhanced performance. The 3-D TCAD simulations indicate that narrow FinFET (20 nm) can exhibit excellent switching characteristics: very low SS of 55 mV/decade, below the 60 mV/decade limit, high on/off current ratio of 10<SUP>10</SUP>, and good current driving capability due to the added 2DEG channel contribution. The maximum transconductance is 350 mS/mm, the drain current reaches 380 mA/mm, and the on resistance is as low as 0.018 <TEX>$\text{m}\Omega \cdot \text {cm}^{2}$</TEX>.</P>
Abnormal drain current (ADC) effect and its mechanism in FD SOI MOSFETs
Yun, J.-G.,Cristoloveanu, S.,Bawedin, M.,Flandre, D.,Lee, Hi-Deok IEEE 2006 IEEE electron device letters Vol.27 No.2
A new type of abnormal drain current (ADC) effect in fully depleted (FD) silicon-on-insulator (SOI) MOSFETs is reported. It is found that the drain current becomes abnormally large for specific front- and back-gate voltages. The drain current exhibits a transient effect due to the floating body behavior and no longer follows the conventional interface coupling theory for these specific front- and back-gate bias conditions. It is shown that the ADC can be generated by the combination of gate-induced drain leakage, transient effects, and parasitic bipolar transistor action in FD SOI MOSFETs.
High-Performance GaN-Based Nanochannel FinFETs With/Without AlGaN/GaN Heterostructure
Ki-Sik Im,Chul-Ho Won,Young-Woo Jo,Jae-Hoon Lee,Bawedin, Maryline,Cristoloveanu, Sorin,Jung-Hee Lee IEEE 2013 IEEE transactions on electron devices Vol.60 No.10
<P>Two types of fin-shaped field-effect transistors (FinFETs), one with AlGaN/GaN heterojunction and the other with heavily doped heterojunction-free GaN layer operating in junctionless mode, have been fabricated and characterized. The threshold voltages of both devices shift toward positive direction from large negative value as the fin width decreases. Both devices exhibit high ON-state performance. The heterojunction-free GaN FinFETs show superior OFF-state performance because the current flows through the volume of the GaN channel layer, which can be fully depleted. The proposed GaN nanochannel FinFETs are very promising candidates not only for high performance, but also for high power applications.</P>
Extended Analysis of the <tex> $Z^{2}$</tex> -FET: Operation as Capacitorless eDRAM
Navarro, Carlos,Lacord, Joris,Parihar, Mukta Singh,Adamu-Lema, Fikru,Duan, Meng,Rodriguez, Noel,Cheng, Binjie,El Dirani, Hassan,Barbe, Jean-Charles,Fonteneau, Pascal,Bawedin, Maryline,Millar, Campbell Institute of Electrical and Electronics Engineers 2017 IEEE transactions on electron devices Vol.64 No.11
<P>The Z(2)-FET operation as capacitorless DRAM is analyzed using advanced 2-D TCAD simulations for IoT applications. The simulated architecture is built based on actual 28-nm fully depleted silicon-on-insulator devices. It is found that the triggering mechanism is dominated by the front-gate bias and the carrier's diffusion length. As in other FB-DRAMs, the memory window is defined by the ON voltage shift with the stored body charge. However, the Z(2)-FET's memory state is not exclusively defined by the inner charge but also by the reading conditions.</P>
Ultra-low power 1T-DRAM in FDSOI technology
El Dirani, H.,Lee, K.H.,Parihar, M.S.,Lacord, J.,Martinie, S.,Barbe, J-Ch.,Mescot, X.,Fonteneau, P.,Broquin, J.-E.,Ghibaudo, G.,Galy, Ph.,Gamiz, F.,Taur, Y.,Kim, Y.-T.,Cristoloveanu, S.,Bawedin, M. ELSEVIER 2017 MICROELECTRONIC ENGINEERING Vol.178 No.-
<P><B>Abstract</B></P> <P>A systematic study of a capacitorless 1T-DRAM fabricated in 28nm FDSOI technology is presented. The operation mechanism is based on band modulation. The Z<SUP>2</SUP>-FET memory cell features a large current sense margin and small OFF-state current at 25°C and 85°C. Moreover, low power consumption during state ‘1’ writing is achieved with ~0.5V programming voltage. These specifications make the Z<SUP>2</SUP>-FET an outstanding candidate for low-power eDRAM applications.</P> <P><B>Graphical abstract</B></P> <P>[DISPLAY OMISSION]</P>