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박은석(Eun-Suk Park),장나은(Na-Eun Zang),김주호(Ju-Ho Kim) 대한전자공학회 2007 대한전자공학회 학술대회 Vol.2007 No.7
As technology scales into sun-90㎚ domain, manufacturing variation become an increasingly significant portion of circuit delay. Therefore, delays must be modeled as statistical distribution during both analysis and optimization. This thesis applies incremental, parametric statistical static timing analysis(SSTA) to perform gate sizing with a required yield. The proposed algorithm sized gates which has higher criticality yielded by utilizing probability of critical path and considering path correlation. The result verified an effectiveness of the delay optimization by gate sizing.
저전력 설계를 위한 경로 상관관계를 고려한 확률적 글리치 예측 및 제거 방법
김유세(You-Se Kim),장나은(Na-Eun Zang),김주호(Ju-Ho Kim) 대한전자공학회 2007 대한전자공학회 학술대회 Vol.2007 No.7
With the growth of CMOS process technology, the influence of process variations during manufacturing becomes increasingly important. There are limitations which consider process variations effectively with the previous static timing analysis methods. The proposed algorithm estimates the glitch occurrence probability by the forward and backward propagating with tightness probability calculation. While glitch occurrence probability calculating. the path correlation information is considered for accurate result. Then gate down sizing operation is executed for glitch removal with Glitch Removal Factor.
이승연(Seung-Yeon Lee),장나은(Na-Eun Zang),김주호(Ju-ho Kim) 대한전자공학회 2007 대한전자공학회 학술대회 Vol.2007 No.7
As technology scales to smaller dimensions, increasing process variation, coupling induced delay variations make delay optimization and signal integrity extremely challenging. In this thesis, under statistical timing analysis, we considered crosstalk to be statistical value instead of deterministic value. A heuristic algorithm sizing gate that has higher priority is proposed for avoiding crosstalk considering statistical timing analysis.