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정전압형 전자식 안정기 회로의 고조파 저감을 위한 PFC회로의 설계
이현무(H.M.Lee),고강훈(K.H.Koh),고희석(H.S.Koh),이현우(H.W.Lee) 한국조명·전기설비학회 2003 한국조명·전기설비학회 학술대회논문집 Vol.2003 No.-
In this paper, a PFC(Power Factor Correction) electronic ballast with constant voltage-fed is proposed. The proposed PFC electronic ballast is combined of a High-efficiency boost converter and a conventional half bridge inverter. It is proved that the ripple of input-current and the input-current"s harmonic of the proposed PFC electronic ballast are reduced using the voltage divider and soft-switching technique. It is demonstrated that simulation results for 40[W] fluorescent lamp correspond with theoretical analysis.