http://chineseinput.net/에서 pinyin(병음)방식으로 중국어를 변환할 수 있습니다.
변환된 중국어를 복사하여 사용하시면 됩니다.
이영근(Young-Geun Lee),이중목(Joong-Mok Lee),안병규(Byung-Gyu Ahn),정찬민(Chan-Min Jung),정기석(Ki-Seok Chung),정정화(Jong-Wha Chong) 대한전자공학회 2006 대한전자공학회 학술대회 Vol.2006 No.11
Modern DSP’s commonly run a set of complicated algorithms which take long run time and high power consumption. Accelerating IP’s are often employed to reduce the execution time and the power consumption. However, as the complexity and the variability of the DSP algorithms are growing, more and more accelerating IP’s are required. Since such specialized fixed IP’s are hard to design and debug, DSP’s with multiple accelerating IP’s are very likely to have a very poor time-to-market and an unacceptably high area cost. To improve the time-to-market and the area efficiency, dynamically reconfigurable DSP architectures have gained a lot of attention lately. Dynamically reconfigurable DSP’s typically have one (or two) multi-functional DSP accelerator which executes different, yet similar multiple core computations for a set of DSP algorithms. With this type of dynamically reconfigurable DSP accelerators, the time to market and the area/power efficiency of the DSP designs can be improved significantly.