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Well-trimmed 위상검출기를 이용한 클럭 및 데이터 복구회로 설계
유순건(Sun-Geon Yoo),장송철(Song-Chul Jang),이상갈(Sang-Kil Lee),조경록(Kyoung-Rok Cho) 대한전자공학회 2007 대한전자공학회 학술대회 Vol.2007 No.7
In this paper, we designed CDR (clock data recovery) circuit using the proposed well-trimmed PD (phase detector). The proposed PD makes up/down signals for veo (voltage controlled oscillator) comparing the data and clock at 3-points that are rising/falling edge of the clock and rising edge of the data. The conventional PD controls VCO using the width of output pulse. However, the proposed well- trimmed PD regulates the VCO with the number of output pulse that controls VCO precisely. The CDR is implemented using a 0.18㎛ CMOS process. under 1.8V supply.