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표준 CMOS 공정에서의 LDMOS를 이용한 고속 레벨시프터 설계
서해준(Hae-Jun Seo),안종복(Jong-Bok Ahn),유기주(Gi-Ju Ryu),조태원(Tae-Won Cho) 대한전자공학회 2007 대한전자공학회 학술대회 Vol.2007 No.11
This paper proposes a new high-speed level shifter using the LDMOS(Laterally Diffused MOS) in the standard CMOS process. The LDMOS is a standard MOSFET device in a 0.18㎛ CMOS process without adding extra mask or process step to realize it. A level shifter uses 5V LDMOSs as voltage clamps to protect 1.8V NMOS switches from high voltage stress the gate oxide. Also, level-up transition from 1.8V to 5V takes only 3㎰ in time. These circuits do not consume static DC power, therefore they are very suitable for low-power and high-speed interfaces in the deep sub-quarter-micron CMOS technologies.