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3-3.5㎓ 대역폭 지원을 위한 오류 보상 듀티 주기 검출기를 구현한 듀티 주기 교정기
이민섭(MinSeop Lee),박현수(HyunSu Park),심진철(JinCheol Sim),권영욱,전진우(JinWoo Jeon),유정식(Jeongsik Yoo),박수호(SooHo Park),김철우(ChulWoo Kim) 대한전자공학회 2020 대한전자공학회 학술대회 Vol.2020 No.8
High-speed memory interface system such as double data rate(DDR) memories require an exact 50% duty cycle system clock for optimal valid data window. This paper presents a duty cycle corrector (DCC) using error compensate duty cycle detector(DCD). The proposed DCC consists of a DCD which implemented error detecting and correcting function, a duty-cycle adjuster, controller and output buffer. The proposed DCC circuit has been implemented and fabricated in a 28-nm CMOS process and occupies 2742<SUP>2</SUP>. The acceptable input clock frequency is from 3㎓ to 3.5㎓ and acceptable duty cycle variation is ±20%. The measured maximum duty-cycle error for the 50% duty-rate is 3.8%.