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차세대 메모리를 위한 병렬적 Double Error Correcting BCH 복호기 설계에 관한 연구
최사라(Sara Choi),나태희(Taehui Na),송병규(Byungkyu Song),김정필(Jung Pill Kim),강승혁(Seung H. Kang),정성욱(Seong-Ook Jung) 대한전자공학회 2015 대한전자공학회 학술대회 Vol.2015 No.6
As the technology node scales down aggressively, it is hard to guarantee the reliability of memory due to the high occurrence of soft errors. Therefore, ECC is generally adopted in the memory system to improve the reliability. Especially for emerging memories, such as ReRAM, PRAM, and STT-MRAM, they usally uses Double Error Correction (DEC) BCH code because this code has relatively low overhead of read latency and circuit complexity. To reduce more read latency, parallel BCH decoding altorihms are proposed recently. In this paper, two ways of implementation for parallel BCH decoding algorithm are compared in terms of delay, area and power.