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Kickback Noise 저감 비교기를 사용한 고속의 8-bit SAR ADC
곽호진(Hojin Kwark),손혁태(Hyeoktae Son),고형호(Hyoungho Ko) 대한전자공학회 2022 대한전자공학회 학술대회 Vol.2022 No.11
This paper proposes an 8-bit successive approximation register analog to digital converter (SAR ADC) with a kickback noise reduction comparator. The effect of kickback noise increases due to the high impedance of CDAC with small unit capacitors for high-speed operation. This work uses kickback noise reduction comparators to reduce its influence and consequently improve the effective b (ENOB) performance of the SAR ADC. It is implemented in 180nm CMOS process with a 1.8 V power supply, and simulated in Cadence Spectre ADE L.
PVT variation에 강인한 Pseudo-Resistor가 적용된 방사선 검출기
남기배(Gibae Nam),유무경(Mookyoung Yoo),손혁태(Hyeoktae Son),김경환(Kyounghwan Kim),위지향(Jihyang Wi),손민혁(Minhyeok Son),최만혁(Manhyeok Choi),유인주(Inju Yu),고형호(Hyoungho Ko) 대한전자공학회 2024 대한전자공학회 학술대회 Vol.2024 No.6
In this paper, we propose a radiation detector incorporating a pseudo-resistor (PR) resilient to PVT variation. To mitigate the equivalent noise charge (ENC) originating from the detector system noise, we designed a low-noise amplifier. We implemented the robust PR with resistance to PVT variations in a compact form and integrated it into the charge sensitive amplifier (CSA) feedback structure. The proposed circuit is designed using a 0.18 μm CMOS process and operates at a supply voltage of 3.3 V. The core amplifier of the radiation detector utilizes a cascode structure with a voltage gain of 86.7 dB and a bandwidth of 37.0 MHz. The input referred noise is 8 nV/√Hz at 1 kHz. The PR is implemented with a small area of 125×100 μm², achieving a large resistance of 250 MΩ. The standard deviation of the PR resistance due to process mismatch is 25 MΩ, demonstrating resilience to process variations. When Si beta particles with an energy of 17 keV are incident on the radiation detector, the ENC for channel 1 using a 50 fF feedback capacitor is 376.9 e<SUP>-</SUP> rms with an SNR of 13.1. For channel 2 using a 100 fF feedback capacitor, the ENC is 325.9 e<SUP>-</SUP> rms with an SNR of 14.3.
Leadless 페이스메이커용 심전도 측정 및 자극 신호 발생 회로
김경환(Kyounghwan Kim),유무경(Mookyoung Yoo),강상균(Sanggyun Kang),진병관(Byeongkwan),손혁태(Jin, Hyeoktae),남기배(Son, Kibae Nam),안승민(Seungmin Ahn),위지향(Jihyang Wi),고형호(Hyoungho Ko) 대한전자공학회 2023 대한전자공학회 학술대회 Vol.2023 No.6
The electrocardiogram (ECG) sensing and pacing pulse generating circuit is a vital feature of the leadless pacemaker, which is an implantable device designed to regulate the hearts rhythm. Unlike traditional pacemakers, this device is placed directly inside the heart, without the need for a lead wire. The ECG sensing feature enables the pacemaker to monitor the hearts electrical activity, which allows it to detect any irregularities in the hearts rhythm. The device then adjusts the pacing rate of the pacemaker to ensure that the heart beats at a regular and consistent rate. The pacing pulse generating circuit delivers electrical stimulation to the heart to improve its function and reduce the risk of heart failure. The pacemaker can be programmed to provide different levels of stimulation, depending on the patients specific needs. To accomplish low noise characteristic and low power consumption, a current-feedback instrumentation amplifier (CFIA) is adopted In the ECG sensing channel, a 60-Hz notch filter is adopted to eliminate powerline interface (PLI). The input-referred noise is 3.69 VRMS and the power consumption are 4.5 μW to 19.4 μW. This low-power consumption characteristic increases the efficiency of the battery in the proposed leadless pacemaker.