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Current Adjusting Auto Zeroing Multipath Operational Amplifier
Min-Hyeok Son(손민혁),Moo-Kyoung Yoo(유무경),Hyeok-Tae Son(손혁태),Kyoung-Hwan Kim(김경환),Ji-Hyang Wi(위지향),Gi-Bae Nam(남기배),Man-Hyeok Choi(최만혁),In-Ju Yu(유인주),Hyung-Ho Ko(고형호) 대한전자공학회 2024 대한전자공학회 학술대회 Vol.2024 No.6
This paper proposes a circuit for reducing lowfrequency noise and offset by applying a ping-pong structure and multipath structure based on current adjusting auto zeroing (CAAZ). CAAZ differs from two prominent auto zeroing techniques by not having an auto zeroing cap in the signal path but existing in the folded cascode stage. This distinction addresses issues such as increased thermal noise due to input signal division and insufficient gain leading to residual offset components in conventional input auto zeroing. Moreover, it can resolve the limited gain issue of output auto zeroing. By applying a multipath structure, the paper suggests using CAAZ ping-pong and integrator in the low-frequency path, while using single-ended differential difference amplifier with a class AB output stage in the high-frequency path for power savings, proposing a low-frequency noise reduction amplifier with a wider bandwidth. A CAAZ multipath amplifier was fabricated using a 0.18 μm TSMC complementary metal-oxide-semiconductor (CMOS) process. The proposed amplifier consumes 0.263 mW with a 1.8 V supply and has an active area of 0.493 mm2. It achieves a unit gain bandwidth (UGBW) of 4.155 MHz, an input referred noise of 29.36 nV/√Hz, and a noise efficiency factor (NEF) of 12.3.
이중 slew-rate boosting 회로를 사용한 저잡음 다중경로 증폭기 설계
위지향(Ji-Hyang Wi),유무경(Moo-Kyoung Yoo),김경환(Kyoung-Hwan Kim),손혁태(Hyeok-Tae Son),남기배(Gi-Bae Nam),손민혁(Min-Hyeok Son),최만혁(Man-Hyeok Choi),유인주(In-Ju Yoo),고형호(Hyoung-Ho Ko) 대한전자공학회 2024 대한전자공학회 학술대회 Vol.2024 No.6
This paper proposes a low-noise multipath operational amplifier with double slew rate enhancement circuit. The proposed circuit consists of a rail-to-rail input stage applied to two auxiliary circuits for improve the slew rate and settling time. The proposed circuit is designed in a 0.18 μm CMOS technology. It achieves 148.4 dB DC gain and 8.1 MHz unity-gain bandwidth. The positive slew-rate of the amplifier has increased from 14.09 V/μs to 21.94 V/μs and the negative slew-rate has increased from 12.34 V/μs to 23.34 V/μs. The proposed amplifier dissipates 825 uW from a 3.3 V supply voltage.