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Fractional spur를 억제한 single-PLL 구조의 Fractional-N 주파수 합성기
최정민(Jeong-Min Choi),양홍준(Hong-Jun Yang),배영빈(Young-Bin Bae),최영식(Young-Shig Choi) 대한전자공학회 2006 대한전자공학회 학술대회 Vol.2006 No.11
In this paper, the fractional-N phase locked loop (PLU architecture for locking time reduction and fractional spur suppressing is proposed based on the adaptive bandwidth and capacitance scaling scheme. The adaptive bandwidth is controlled by charge pump current. The effective capacitance of loop filter can be scaled up/down depending on the lock status. It has been simulated by HSPICE in a CMOS 0.35㎛ process, and shows that locking time is 50㎲ with the loop filter 3㎋ and 200㎊ capacitors, and 2.1㏀ resistor.