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저전력 설계를 위한 경로 상관관계를 고려한 확률적 글리치 예측 및 제거 방법
김유세(You-Se Kim),장나은(Na-Eun Zang),김주호(Ju-Ho Kim) 대한전자공학회 2007 대한전자공학회 학술대회 Vol.2007 No.7
With the growth of CMOS process technology, the influence of process variations during manufacturing becomes increasingly important. There are limitations which consider process variations effectively with the previous static timing analysis methods. The proposed algorithm estimates the glitch occurrence probability by the forward and backward propagating with tightness probability calculation. While glitch occurrence probability calculating. the path correlation information is considered for accurate result. Then gate down sizing operation is executed for glitch removal with Glitch Removal Factor.