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화합물-실리콘 이종 반도체 융합 공정에 따른 실리콘 웨이퍼 뒷면 비소 오염 최소화 연구
임성규(Sung-Kyu Lim),김도균(Do-Kywn Kim),황해철(Hae-Chul Hwang),김진수(Jin-Su Kim),신찬수(Chan-Soo Shin),이희덕(Hi-Deok Lee),김대현(Dae-Hyun Kim) 대한전자공학회 2016 대한전자공학회 학술대회 Vol.2016 No.6
In this paper, we have investigated a pathway to mitigate the arsenic (As) cross-contamination on a back side Si wafer during GaAs growth by metal-organic chemical vapour deposition (MOCVD). Without a proper protocol doing a III-V on Si heterogeneous epitaxy, We have observed high levels of the As concentration on the back side Si wafer, easily in excess of 1 × 10<SUP>20</SUP> atoms/㎤ by secondary ion mass spectrometry (SIMS) analysis and 10<SUP>15</SUP> atoms/㎠ by total reflection X-ray fluorescence (TXRF) analysis, after GaAs growth on Si. This known level of contamination on wafers would disqualify them for fabrication in existing Si VLSI FABs. In order to mitigate the As cross-contamination, we have proposed a SiO2 protection layer on the back side of the Si wafer. From both SIMS and TXRF analysis, the proposed scheme has dramatically lowered the back side as concentration to 1.5 × 10<SUP>16</SUP> atoms/㎤ by SIMS and 1.0 × 10<SUP>10</SUP> atoms/㎠ by TXRF.