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Kickback Noise 저감 비교기를 사용한 고속의 8-bit SAR ADC
곽호진(Hojin Kwark),손혁태(Hyeoktae Son),고형호(Hyoungho Ko) 대한전자공학회 2022 대한전자공학회 학술대회 Vol.2022 No.11
This paper proposes an 8-bit successive approximation register analog to digital converter (SAR ADC) with a kickback noise reduction comparator. The effect of kickback noise increases due to the high impedance of CDAC with small unit capacitors for high-speed operation. This work uses kickback noise reduction comparators to reduce its influence and consequently improve the effective b (ENOB) performance of the SAR ADC. It is implemented in 180nm CMOS process with a 1.8 V power supply, and simulated in Cadence Spectre ADE L.