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- 저자 : Yintang Li (검색결과 3 건)
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Biaxial creep property of ethylene tetrafluoroethylene (ETFE) foil
Yintang Li,Minger Wu 국제구조공학회 2015 Structural Engineering and Mechanics, An Int'l Jou Vol.54 No.5
Ethylene tetrafluoroethylene (ETFE) foil is a novel structural material which has being used in shell and spatial structures. This paper studies biaxial creep property of ETFE foil by creep tests and numerical simulation. Biaxial creep tests of cruciform specimens were performed using three stress ratios, 1:1, 2:1 and 1:2, which showed that creep coefficients in biaxial tension were much smaller than those in uniaxial one. Then, a reduction factor was introduced to take account of this biaxial effect, and relation between the reduction factor and stress ratio was established. Circular bubble creep test and triangle cushion creep test of ETFE foil were performed to verify the relation. Interpolation was adopted to consider creep stress and reduction factor was involved to take account of biaxial effect in numerical simulation. Simulation results of the bubble creep test embraced a good agreement with those measuring ones. In triangle cushion creep test, creep displacements from numerical simulation showed a good agreement with those from creep test at the center and lower foil measuring points.
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Li, Yani,Zhu, Zhangming,Yang, Yintang,Zhang, Chaolin The Korean Institute of Power Electronics 2015 JOURNAL OF POWER ELECTRONICS Vol.15 No.4
This study presents an input-powered high-efficiency interface circuit for energy harvesting systems, and introduces a zero standby power design to reduce power consumption significantly while removing the external power supply. This interface circuit is composed of two stages. The first stage voltage doubler uses a positive feedback control loop to improve considerably the conversion speed and efficiency, and boost the output voltage. The second stage active diode adopts a common-grid operational amplifier (op-amp) to remove the influence of offset voltage in the traditional comparator, which eliminates leakage current and broadens bandwidth with low power consumption. The system supplies itself with the harvested energy, which enables it to enter the zero standby mode near the zero crossing points of the input current. Thereafter, high system efficiency and stability are achieved, which saves power consumption. The validity and feasibility of this design is verified by the simulation results based on the 65 nm CMOS process. The minimum input voltage is down to 0.3 V, the maximum voltage efficiency is 99.6% with a DC output current of 75.6 μA, the maximum power efficiency is 98.2% with a DC output current of 40.4 μA, and the maximum output power is 60.48 μW. The power loss of the entire interface circuit is only 18.65 μW, among which, the op-amp consumes only 2.65 μW.
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Yani Li,Zhangming Zhu,Yintang Yang,Chaolin Zhang 전력전자학회 2015 JOURNAL OF POWER ELECTRONICS Vol.15 No.4
This study presents an input-powered high-efficiency interface circuit for energy harvesting systems, and introduces a zero standby power design to reduce power consumption significantly while removing the external power supply. This interface circuit is composed of two stages. The first stage voltage doubler uses a positive feedback control loop to improve considerably the conversion speed and efficiency, and boost the output voltage. The second stage active diode adopts a common-grid operational amplifier (op-amp) to remove the influence of offset voltage in the traditional comparator, which eliminates leakage current and broadens bandwidth with low power consumption. The system supplies itself with the harvested energy, which enables it to enter the zero standby mode near the zero crossing points of the input current. Thereafter, high system efficiency and stability are achieved, which saves power consumption. The validity and feasibility of this design is verified by the simulation results based on the 65 nm CMOS process. The minimum input voltage is down to 0.3 V, the maximum voltage efficiency is 99.6% with a DC output current of 75.6 μA, the maximum power efficiency is 98.2% with a DC output current of 40.4 μA, and the maximum output power is 60.48 μW. The power loss of the entire interface circuit is only 18.65 μW, among which, the op-amp consumes only 2.65 μW.
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