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임낙형 한국개혁신학회 2003 한국개혁신학 Vol.14 No.-
Schweitscher hat nach Leben-Jesu-Forschung "Von Reimarus zu Wrede" (1906) geschrieben. Nach seinem Forschung war Jesus in dem Neuen Testament nicht der Auferstandene in der geschichtlichen Wirklichkeit, sondern nur in den Geitsten seiner Juenger. Jesus wollte Gottesreich in der Welt aufbauen, aber konnte nicht und war gestorben. Schweitscher hat darum nur ein Lebensform im Geschick Jesu herausgefunden. Er wollte auch das Lebenform Jesu auf eigene Weise folgen und ein Reich Gottes aufbauen. Hier wird eine Frage gestellt: Hat sein Lebensstil ohne Grund doch recht? Ja, jeder kann auf eigene Weise leben. Aber soche Lebensweise ist nicht die christliche Ethik. Sondern die christliche Ethik hat den christologischen Grund. Vor allem stellen wir fest, dass die Auferstehunggeschenhen Jesu die geschichtliche Wirklichkeit wer und ist, und der Grund der christlichen Ethik. Weil die in der Bibel erklaete uferstehungereignis Jesu als geschichtliche Wirklichkeit bewiesen wird. Der Auferstandene ist unser Herr, unser Koenig und unser Gott. Darum die Ethik Jesu, der in seinenm Geschick gezeigt hat und in seinem Wort befohlen hat, ist die Offenbarungsethik, die absolute Ethik und die endzeitliche Ethik. Darum die christliche Ethik ist allgemeingueltig.
宋洛雲 弘益大學校 1990 弘大論叢 Vol.22 No.2
In this paper, the feasibility of DSP-related IC chip development is studied with respect to world market and technology. It is found that the DSP-related areas, such as HDTV, ISDN, will lead the world semiconductor market in near future. To step up with this fast R&D in this area, it is belived that the top-down design capability, including the cooperation of system designers and semiconductor designers, is obligatory and urgent. Several devices such as codec chips are recommended for development.
송낙운 弘益大學校 科學技術硏究所 1994 科學技術硏究論文集 Vol.5 No.-
In this work, 2D FIR DF is designed and simulated by C. VHDL languages. Designed two-dimensional digital filter mainly consists of one-dimensional digital filter and line memory. Once digital filter coefficients are represented by CSD(Canonical signed Digit) formats, multipliers are realized by hardwired-shifting methods. To speed up the 1D DF block, carry-save adder in each tap and Manchester adder in every 1D DF are adopted. The designed filter is performed up to 30 MHZ and related layouts are now in progress by Berkeley CAD tools.
宋洛雲,金大硯 弘益大學校 科學技術硏究所 2001 科學技術硏究論文集 Vol.12 No.-
In this paper, the architecture of turbo codec for IMT-2000 system is proposed. The architecture consist of address generator by on-the-fly method and turbo interleaver & encoder using modifed-shift register and memory-saving decoder unusing external RAM. The suggested architecture for turbo codec using in the CDMA2000 standard for IMT-2000 is simulated by C++, VHDL using IDEC C-632 standard cell library. It shows improved coding gain with various code rate & interleaver block size.
宋洛雲 弘益大學校 科學技術硏究所 1992 科學技術硏究論文集 Vol.2 No.-
In this work, the VLSI design framework is made by establishing design methodology with respect to the corresponding design levels. To achieve this, the related design CAD softwares, i.e., critical path calculation, schedulingr by simulated annealing, VHDL works, are developed at each design level. The MPC chip is made by the prepared CAD design environment, and presently the data paths such as Booth multiplier, ALU, are designed.
Subband filtering에 의한 코덱의 설계에 관한 연구
宋洛雲,李鎔旭 弘益大學校 科學技術硏究所 1997 科學技術硏究論文集 Vol.8 No.-
In this paper, the architecture of SBC with SBF and BTSVQ for image processing is designed. The SBF consists of filter calculation and memory, where multiplication is implemented by CSD and QMF filter is used for LPF, HPF. The operation of designed architecture is confime for given images. Here, in spite of the increase of average distortion, blocking effect is found to be decreased.