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RISS 인기검색어
- 검색키워드
- 저자 : Mahsa Piltan (검색결과 4 건)
- 무료
- 기관 내 무료
- 유료
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Design FPGA-Based Chattering-free Sliding Mode Controller for PUMA Robot Manipulator
Mahsa Piltan,Abdolwahab Kazerouni,Ali Rafie 보안공학연구지원센터 2015 International Journal of Hybrid Information Techno Vol.8 No.12
Design of a robust controller for multi input-multi output (MIMO) nonlinear uncertain dynamical system can be a challenging work. This research focuses on the design and analysis of a high performance chattering free PD plus PD partly sliding mode controller in presence of uncertainties. In this research, sliding mode controller is a robust and stable nonlinear controller, which selected to control of robot manipulator. The proposed approach effectively combines of design methods from switching sliding mode controller, and linear Proportional-Derivative (PD) control to improve the performance, stability and robustness of the sliding mode controller. To reduce the chattering with respect to stability and robustness; linear controller is added to the switching part of the sliding mode controller. The linear controller is to reduce the role of sliding surface slope and switching (sign) function. To improve the flexibility, design high speed and low cost controller, micro-electronic device (FPGA-Based) controller is introduced in this research. The proposed design is 30-bits FPGA-based controller for inputs and 35-bits for output. All joints of robot are used to test the controller in simulation environments, using VHDL code for the purpose of simulation in Xilinx. The maximum frequency in FPGA-based design is about 63.6 MHz and the delay time in this design is about 15.7 ns. It is observed that this controller is able to make as a fast response at 15.716 clock period with 63.6 of a maximum frequency and 4.407 for minimum input arrival time after clock. From investigation and synthesis summary, 30.286 for maximum input arrival time after clock with 33.018 frequencies, this design has 15.716 delays for each controller to 46 logic elements and the offset before CLOCK is 55.773 for 132 logic gates.
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Research on FPGA-Based Controller for Nonlinear System
Farzin Piltan,Maryam Rahmani,Meysam Esmaeili,Mohammad Ali Tayebi,Mahsa Piltan Hamid Cheraghi,Mohammad R. Rashidian,Arzhang Khajeh 보안공학연구지원센터 2015 International Journal of u- and e- Service, Scienc Vol.8 No.3
Many of linear control applications require real-time operation; higher density programmable logic devices such as field programmable gate array (FPGA) can be used to integrate large amounts of logic in a single IC. This work, proposes a developed method to design PD controller (PDC) with optimal- gains using FPGA. The method used to design PD controller is to design it as digital design Proportional and Derivative controller in parallel through the summer. The proposed design is 32-bits FPGA-based controller (32PDC), which uses 32-bits for each input/output variable. The single joint of robot is used to test the controller in simulation environments, using VHDL code for the purpose of simulation in Xilinx. The same design is coded in MATLAB environment (MPDC) in order to make a comparison with the proposed FPGA-based design. PDC needs 16 clock cycles to complete one action with maximum frequency of 108.5 MHz. 32PDC is able to produce an output in 13.24 MHz with the robot system. Therefore, the proposed controller will be able to control a wide range of the systems with high sampling rate and 75.545 ns delays.
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Research on Oscillation-Free Robust Control for Active Joint Dental Automation
Farzin Piltan,Meysam Esmaeili,Mohammad Ali Tayebi,Mahsa Piltan,Mojtaba Yaghoot,Nasri B. Sulaiman 보안공학연구지원센터 2016 International Journal of Hybrid Information Techno Vol.9 No.11
Design a robust oscillation-free controller for multi input-multi output (MIMO) nonlinear uncertain dynamical system (sensitive dental joint) is the main objective in this research. In this paper, robust sliding mode controller will be selected as a main control technique and linear controller will be design to improve the stability and robustness to control of dental joint. The proposed approach effectively combines of design methods from switching sliding mode controller, and linear Proportional-Integral-Derivative (PID) control to improve the performance, stability and robustness of the sliding mode controller. Conventional sliding mode controller has two important subparts, switching and equivalent. Switching part (discontinuous part) is very important in uncertain condition but it causes chattering phenomenon. To solve the chattering, the most common method used is linear boundary layer saturation method, but this method lost the stability. To reduce the chattering with respect to stability and robustness; linear controller is added to the switching part of the sliding mode controller. The linear controller is to reduce the role of sliding surface slope and switching (sign) function. This controller improves the stability and robustness, reduces the chattering as well and reduces the level of energy due to the torque performance as well.
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Design FPGA-Based Fuzzification Algorithm for Model-free Control Techniques
Farzin Piltan,Maryam Rahmani,Omid Mahmoudi,Meysam Esmaeili,Mohammad Ali Tayebi,Mahsa Piltan,Hamid Cheraghi 보안공학연구지원센터 2016 International Journal of Hybrid Information Techno Vol.9 No.8
Many of fuzzy control applications require real-time operation; higher density programmable logic devices such as field programmable gate array (FPGA) can be used to integrate large amounts of logic in a single IC. This work, proposes a developed method to fuzzifier algorithm with optimal-tunable gains method-using FPGA. The maximum frequency in FPGA-based design is about 72.4 MHz and the delay time in this design is about 13.78 ns. It is observed that this algorithm is able to make as a fast response at 13.78 clock period with 72.4 of a maximum frequency and 2.1 ns for minimum input arrival time after clock. From investigation and synthesis summary, 24.3 for maximum input arrival time after clock with 13.9 MHZ frequencies, this design has 13.78 ns delays for each controller to 46 logic elements and the offset before CLOCK is 82.1 ns.
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