ONO 적층절연막의 전기전도 특성에 관한 연구

정양희,김경민 여수대학교 1998 論文集 Vol.12 No.2

In this paper, the stacked-dielectric layer oxide/nitride/oxide(ONO) is studied to scale down the memory device. Studying the change of composition in ONO layer due to the process condition and the conduction mechanism are investigated. The composition of the oxide film grown through the oxidation of nitride film is analyzed using auger electron spectroscopy(AES). AES results show that oxygen concentration increases at the interface between oxide and nitride layers as the thickness of the top oxide layer increases. When the top oxide film is thicker than 35Å, the concentration of oxygen increases both at the surface of nitride and in the nitride film. As the thickness of the top oxide and nitride increases, the electrical breakdown field increases. Optimum film thickness for scaled stacked-layer dielectric(ONO) is 63Å for nitride and 28Å for top oxide. In this case, maximum electrical breakdown field and leakage current is 18.5[MV/cm] and 8×10??[A], respectively.

L/L LPCVD를 이용한 다층절연막 특성에 관한 연구

정양희 여수대학교 2002 論文集 Vol.17 No.-

The ONO multi dielectric layer oxide-nitride-oxide(ONO) in used to improve electrical capacitance and to scale down the memory device. In this paper, the NO(SiO2/Si3N4) multi-dielectric layer in 0.5μm-scaled DRAM is studied to scale down the memory device. Improvement of the capacitance by reducing the bottom oxide thickness in the nitride deposition with load-lock(L/L) vacuum system is studied. Effective thickness and cell capacitance for SONOS capacitor are studied below 70A˚ thickness range between L/L and non-L/L system. Compared with non-L/L system, the native oxide thickness in the case of L/L system is decreased while capacitance increases about 3~5fF/cell.

다층절연막의 트랩 모델과 Scale down 매캐니즘에 관한 연구

정양희 여수대학교 2002 論文集 Vol.17 No.-

In this paper, the multi dielectric layer oxide-nitride-oxide(ONO) is studied to scale down the memory device. New carrier trapping model for maximum flatband voltage shift of multi layer dielectric film is proposed and compared with experimental data. As a results of curve fitting. Comparing the interface trap, generated in the interface between top oxide layer and nitride layer, with the memory trap in the nitride layer, the mechanism and the limit of scaling down of the ONO system are investigated.

TSIC법을 이용한 MIS 소자의 Mobile 이온에 관한 연구

정양희 여수대학교 1997 論文集 Vol.11 No.2

In this paper mobile ions in SiO₂layer of MOS structures have been investigated with the thermally stimulated ionic current(TSIC) method. In this experiment current due to sodium ion was measured by applying various bias voltage and changing temperature in device, and peak value of the current was obtained in the range of 443 -455˚K. To determine the activation energy from temperature dependence of the measured current peak shape method is used. The activation energy obtained is in the range of 0.43 - eV. Ionic charge in oxide layer is calculated by the TSIC method and measured flat band shift. The good correlation between Q(TSIC) and Q(ΔV FB) is observed.

Avalanche 주입에 따른 질화산화막의 트랩특성에 관한 연구

정양희 麗水水産大學校産業技術硏究所 1997 産業基術硏究所 論文集 Vol.6 No.-

The MIS(Metal-Insulator-Semiconductor) with the nitrided oxide and RTO annealed nitrided oxide are fabricated to investigate the carrier trapping due to avalanche electron injection. Two times turn-around phenomenon of the flatband voltage shift generated by the avalanche electron injection are observed. This shows that electron trapping occurs dominantly in the oxide at the first stage. As the cumulated electron injection increases, the first turn-around phenomena occurs due to a positive charge build-up in the oxide layer. After futher avalanche electron injection the flatband voltage curves turns around once again. This second turn-around phenomena is due to the electrons captured by an acceptor-like trap. A positive charge build-up in the oxide and interface trap density at the mid-gap increase for heavy nitridation(1100℃, 900sec) oxide comparing with lightly nitridation oxide(900℃, 90sec). Interface trap density is measured as 2.23 x 10¹³~ 5.01 x 10¹³[eV-¹cm-²]

TSC법에 의한 MNOS의 memory trap 특성에 관한 연구

정양희,최치영 여수대학교 1998 論文集 Vol.13 No.2

In this paper, C-V measurement and Thermally Stimulated Current(TSC) method were examined to interpret trap distribution and charging and discharging mechanism in a Metal-Nitride-Oxide-Semiconductor(MNOS) device. TSC in MNOS diode consists of four components, the current due to the excitation of carriers trapped in deep levels at or near the nitride-oxide(N-O) interface contribute to the memory effect and was seperated from the others. The charges released N-oO interface trap by TSC was compared with the change of charges calculated from the gate voltage shift before and the TSC measurement. Peak shape method and Heating rate method were applied to determine the trap energy level. The energy level of the memory trap near the N-O interface lies 0.44-0.66[eV] from the bottom of the nitride conduction band, and the frequency factor is 6.58×10³/sec. The good correlation between Q(TSC) and Q(△VFB) is observed.

게이트 산화전 RCA세정 횟수에 따른 Si/SiO₂계의 절연특성에 관한 연구

정양희,유일현,한원열 麗水水産大學校産業技術硏究所 1998 産業基術硏究所 論文集 Vol.7 No.-

The purity of wafer surface is an essential requisite for the successful fabrication of VLSI silicon circuits. The solution used in the cleaning step of silicon wafer surfaces known as "RCA standard clean" has the volume ratios NH₄OH : H₂O₂: H₂O=1:1:5. This RCA cleaning process for bare wafer can affect the state of wafer surfaces. This can cause the degeneration of gate oxide layer. For the investigation of this problem, we measured the Dit(interface trap density) of Si/SiO₂system using the C-V method. The Dit is in the range of 0.89∼2.13×10¹¹[cm-²eV-¹]. This measure is increased proportionally to the number of cleaning times. Leakage current is in the range of 1×10-¹∼1×10(-8)[A] according to the cleaning times, especially, we notice that additional RCA cleaning increases the leakage current in the order of hundred times compared to one times cleaning under 10[V] gate voltage. The electrical breakdown field using the breakdown obtained by I-V method is in the range of 8~12[MV/cm]. This measure is decreased proportionally to the cleaning times. This increment of leakage current by additional RCA cleaning result in the 0.8% decrement of yield. Since cleaning process of before gate oxidation directly affect the device performance and reliability, we think that further investigation is necessary for the clear understanding and of cleaning process.

Fowler-Nordheim 주입하의 MONOS 캐패시터 계면특성

정양희 麗水水産大學校 産業技術硏究所 1996 産業基術硏究所 論文集 Vol.5 No.-

The MONOS capacitor are fabricated to investigate the interface characteristics due to Fowler-Nordheim tunneling injection. Memory effect increases as the thickness of the top oxide increases. Interface trap(top SiO₂ /Si₃N₄) density is measured as ??. Charge centroid is located between top oxide and nitride. Maximum memory effect is obtained under the current stress of 1E-6A at positive gate bias and 1E-7A(20Å) and 1E-8A(10Å) at negative gate bias. Memory effect and interface trap density also increases as the thickness of nitride increases. maximum memory effect obtained under the current stress of 1E-6A at positive gate bias, and 1E-7A at negative gate bias. Carriers captured at nitride could not escape from nitride to gate but be captured at interface(top SiO₂Si₃N₄) traps because of barrier height of top oxide. Therefore, it is expected that the MONOS memory devices enhance memory effect and have a long memory retention characteristic.

불측정 상태변수를 갖는 이산치 다변수계통에 대한 슬라이딩 모드 제어기의 설계

김경민,정양희 여수대학교 1998 論文集 Vol.12 No.2

In this paper, we degined sliding mode controller for discrete-time multivariable systems with unmeasurable state variables. Practical control systems are usually realized by digital computer. And there has existed a gap between the continuously designed VSCS (Variable Structure Control System) and the realized control systems. So, we propose the sliding mode control theory which are extended from continuous VSCS theory for controlling the discrete systems. And the previous sliding mode control theory assumed that the systems have all of measurable state variables. However, in practical systems, all state variables are not measurable. Thus, in this paper, we also investigate the discrete system there not all states are available for switching function synthesis or control. In all the case, computer simulation results are presented to demonstrate the effects of theories.

산화전세정에 따른 표면 Microroughness 및 불량분석에 관한 연구

김경민,유일현,정양희 麗水大學校 産業基術硏究所 1999 産業基術硏究所 論文集 Vol.8 No.-

The purity of wafer surface is an essential requisite for the successful fabrication of VLSI silicon circuits. In the cleaning step, the precleaning(NH₄OH/H₂O₂/H₂O) method has been used. The precleaning process for bare wafer can affect the state of wafer surfaces. It can cause the degeneration of gate oxide layer. For the investigation of this problem, we measured the microroughness of silicon wafer surface using the atomic force microscope(AFM). The microroughness is in the range of 1.1∼1.6Å. The result is increased proportionally to the number of cleaning times. This problem by additional precleaning distributed to edge in the wafer. To avoid th yield drop due to the microroughness, we suggest that the content ratio of precleaning solution is to be at 0.2:1:10 and the cool DI water rinsing should be followed after cleaning step. However, additional cleaning process should be applied carefully to avoid failure even in the optimized precleaning process.