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High reliability and low noise amorphous-silicon gate with novel clock-driving methodology
Chien-Hsueh Chiang,Yiming Li 한국정보디스플레이학회 2014 Journal of information display Vol.15 No.1
In this paper, for the first time, a novel amorphous-silicon thin-film transistor (TFT) gate drive circuit and its successfully improved dynamic characteristics are presented. Not only was the output ripple suppressed; the rate of threshold voltage shift was also reduced by up to 20%. About 50% power-saving was also estimated. The amorphous-silicon gate driver (ASG) circuit was further fabricated, and the measured results show the high practicability of the achieved design.
Yi-Hsuan Hung,Sheng-Chin Hung,Chien-Hsueh Chiang,Yiming Li 한국정보디스플레이학회 2016 Journal of information display Vol.17 No.2
A short rise time, short fall time, and small ripple are required to reduce the misoperation of pixel data voltage and to improve the stable signal processing of a driver circuit. In this study, a novel amorphous silicon gate (ASG) driver circuit consisting of 15 hydrogenated amorphous silicon thin-film transistors (a-Si:H TFTs) and two capacitors was optimized using a thin-film transistor (TFT)-circuitsimulation- based multi-objective evolutionary algorithm on the unified optimization framework . The ASG circuit was optimized for the following given specifications: rise time <0.7 μs; fall time <0.6 μs; ripple peak <6.5 V; clock Ctotal <40 pf; and total TFT widths <6000 μm. The main findings of this study show that the rise time had an 18% reduction and that the fall time, total widths, and clock Ctotal had 7, 17.5, and 9% reductions, respectively.