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높은 선형성을 갖는 2.4㎓ 무선랜용 CMOS 하향 주파수변환기의 설계
신이주(Yi-Joo Shin),김태원(Tae-Won Kim),김복기(Bok-Ki Kim) 대한전자공학회 2007 대한전자공학회 학술대회 Vol.2007 No.7
The mixer is derived from the basic Gilbert cell multiplier. Design methodology is presented to achieve high linearity using source inductance degeneration, current injection, and common mode feedback (CMFB). The RF, LO, and IF port frequencies are 2.4 ㎓, 2.3 ㎓, and 10 ㎒, respectively. The designed mixer requires a 1.8 V supply voltage and consumes 11.7 ㎽ DC power. This mixer has SSB NF of 15.3 ㏈, IIP3 of 1.52 ㏈m and conversion gain of 1.9 ㏈.
5.25 ㎓ CMOS Low Noise Amplifier for WLAN applications
한대훈(Dae-Hoon Han),신이주(Yi-Joo Shin),김태원(Tae-Won Kim),손철호(Chul-Ho Son),김복기(Bok-Ki Kim) 대한전자공학회 2007 대한전자공학회 학술대회 Vol.2007 No.11
In this paper, we present a 5.25 ㎓ CMOS LNA (Low Noise Amplifier) for Wireless LAN applications. A popular cascode topology for LNA design is employed to satisfy both noise and high gain. The PCSNIM (Power constrained simultaneous noise and input matching) technique is applied to achieve simultaneous noise and input matching at any given amount of power dissipation. The simulated results show that both Su and S₂₂ are less than -10㏈ over 5.15 ~ 5.35 ㎓, 1.81㏈ noise figure, -17.4㏈m IIP3 and 17.1㏈ power gain at 5.25 ㎓ while consuming 8.78㎽ DC power using TSMC 0.18㎛ RF CMOS technology. The layout area is 870 x 610㎛².
Cascode 구조의 5.8 ㎓ Wireless LAN 용 CMOS 저잡음 증폭기 설계
손철호(Chul-Ho Son),신이주(Yi-Joo Shin),김태원(Tae-won Kim),한대훈(Dae-Hoon Han),김복기(Bok-Ki Kim) 대한전자공학회 2007 대한전자공학회 학술대회 Vol.2007 No.11
The proposed low noise amplifier design applied to the cascade topology based on TSMC 0.18 ㎛ RF CMOS technology for 5.8 ㎓ WLAN applications. The simulation results show power gain of 16.1 ㏈, noise figure of 1.84 ㏈ and third-order input intercept point of -13.53 ㏈m while dissipates the DC current of 3.9㎃ at supply voltage of 1.8V. The chip die size 835 ×x 598 (㎛²)
2.4㎓ Wireless LAN 용 0.18㎛ CMOS 저잡음증폭기의 설계에 관한 연구
김태원(Tae-won Kim),신이주(Yi-Joo Shin),김복기(Bok-Ki Kim) 대한전자공학회 2007 대한전자공학회 학술대회 Vol.2007 No.7
A 1.8V 2.4㎓ CMOS LNA with PCSNIM technic for WLAN was designed to use for hynix standard 0.18㎛ CMOS process. It’s input and output are all matched to 50ohms with off-chip inductor components‘ The simulation results show that the amplifier achieves 1.43㏈ noise figure, 17㏈ power gain, -13.7㏈m third-order input intercept point. The designed LNA requires a 1.8V supply voltage and consumes 4.95 ㎽ DC Power. The die area is 430 × 250 (㎛).