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It has been studied on the detect and correct of errors occurring in the Process of Keeping and handling of data with the development in data communication field and data base field. Especially, the errors on the process of reception and transmision in data communication field are effective when they are detected and corrected immediately. The writer tried to convert the data using u-processor into Hamming code, and tried to find out the way which can revert the Hamming code to be received to the original data by detecting the presence of the errors and correcting them immediately. The writer concentrated on the drawing up of encoding program and detecting program.
In this study, two-dimension hamming code has been applied in detection and correction multi bit error on the binary string. Condition of multi bit errors is divided into 5 types, and correction measures are provided for each type, and each measure is programmed to correct the input data.
This paper describes a development of the PLD design tool. To design digital circuit with PLDs, several steps in the developed PLD design tool are needed such as Boolean description step, pin map step, FUSE map and JEDEC steps…etc. Especially, we have considered the PLD partition to design large digital circuits with PLDs developed the limited partition algorithms based on the PLD device fitting and compared with the results of a another PLD design tool(PALASM). Also, we have proved that the developed PLD design tool is successfully implemented by the connection with a PLD writer (ALL-07), in the case of design digital circuits.
Existing, widely used industrial controller programmable logic controller (PLC) using the high cost and maintenance was a difficult problem. In addition, the network configuration was not easy. Thus, the filter press by video remote control and management to improve productivity and shorten maintenance time. Variety of smart devices (smart phones, iPad, tablet PC, etc.) Remote control is possible by utilizing the existing controlled by the PLC addresses maintenance and improved performance compared to that of possible filter press control and management system was developed.
This study investigates the most efficient way of managing traffic signal system by installing 2 sensors on both lanes of each direction. In order to achieve efficiency of traffic, these sensors are devised to sense flows of traffic on each lane. If the sensor on one side of the lane. senses no traffic, it deems that there is no traffic in waiting, and it skips green light and proceeds to the next direction. If only front sensor senses traffic, it gives short signal, and if both sides of sensor sense traffic, it is devised to give long signal, in order to maximise the efficiency of traffic flow. In this study, a multi-signal generating circuit and a variable clock signal switching circuit were designed for simulations, and result from the simulation was found satisfactory
Generally, digital circuit has been designed on the basis that the result by simulated by the arranged tool for plan. In other words, for simulations gate or library sent by IC Cooperation is connected through the schematic editor and the necessary signals for input such as clock signal are supplied. In this way they study the result of simulation. But in this study I found out a new simulation method which is more efficient than the older one in the past. I put a state diagram and state table into tool for design in order to avoid the complexity of circuit input such as combination logic circuit or sequential logic circuit. Then, symbols produced in this way were applied to the schematic editor for simulation.
This paper describes a development of the PLD design tool in considering with a device fitting. To design digital circuit with PLDs, several steps in the developed PLD design tool are needed such as Boolean description step, pin map step, FUSE map and JEDEC steps ... etc. Especially, we have considered the device fitting to design large digital circuits with PLDs developed the device fitting algorithms based on the PLD device fitting and compared with the results of a another PLD design tool(PALASM). Also, we have proved that the developed PLD design tool is successfully implemented by the connection with a PLD writer(ALL-07), in the case of design digital circuits.
For the purpose of the traffic smoothness of the crossroad, this paper construct a car sensor, that classify the heavy traffic direction into the smoothness direction, in the smoothness direction. If the sensor sense no signal the traffic continuously in the heavy traffic. Therefore the traffic increment efficiently.And using by the Generic Array Logic device, we design the traffic controller with small size and economically.
This paper describes a design of dynamic memory control state sequencer using a device partition technique. In specially, we have considered the device partition technique to design large digital circuits with PLDs that limited device partition algorithms based on the PLD device partition, critical path in combinational logic circuit and cycle path in sequential logic circuit. Also, we have proved that the design dynamic memory control state sequencer is successfully implemented using by PLD writer(ALL-07).