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Prognostic Significance of Perirenal Infiltration in Renal Cell Carcinoma (<7 cm)
오성엽,정재일,윤장호,강동일,조흥래 연세대학교의과대학 2012 Yonsei medical journal Vol.53 No.5
Purpose: Pathologic stage is the most accurate prognostic factor of renal cell carcinoma. We evaluated whether perirenal fat infiltration is a significant factor in tumors 7 cm or less in size. Materials and Methods: We retrospectively reviewed the record of 164 cases of tumors 7 cm or less in size. We divided the patients into two groups according to the presence of perirenal fat infiltration (group A, pT1; group B, pT3a). We evaluated relationships, recurrence-free survival and disease-specific survival according to clinicopathologic parameters. Statistical differences were calculated by log-rank test. Results: A total 131 patients were included in group A, with a mean age of 55.8 years, average tumor size was 4.2 cm, and a mean follow-up period of 43 months. Group B included 33 patients, with a mean age of 55.9 years, an average tumor size of 4.1 cm, and a mean follow-up period of 38 months. There was no significant difference in disease-specific survival; however, recurrence-free survival showed significantly different between two groups (group A: 95.5%, group B: 84.4%). Conclusion: In this study, perirenal fat infiltration proved to be an independent prognostic factor for predicting disease-free survival in patients with tumors of 7 cm or less in size. Therefore, as this study showed, the presence of perirenal fat infiltration requires stricter follow-up planning,even in small renal cell carcinoma.
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이정수,오성엽,류재수,유준서,Lee, Jung-soo,Oh, Sung-yeop,Ryu, Jae-su,Yoo, Jun-seo 한국재료학회 2019 한국재료학회지 Vol.29 No.2
Recently, metal cases are widely used in smart phones for their luxurious color and texture. However, when a metal case is used, electric shock may occur during charging. Chip capacitors of various values are used to prevent the electric shock. However, chip capacitors are vulnerable to electrostatic discharge(ESD) generated by the human body, which often causes insulation breakdown during use. This breakdown can be eliminated with a high-voltage chip varistor over 340V, but when the varistor voltage is high, the capacitance is limited to about 2pF. If a chip capacitor with a high dielectric constant and a chip varistor with a high voltage can be combined, it is possible to obtain a new device capable of coping with electric shock and ESD with various capacitive values. Usually, varistors and capacitors differ in composition, which causes different shrinkage during co-firing, and therefore camber, internal crack, delamination and separation may occur after sintering. In addition, varistor characteristics may not be realized due to the diffusion of unwanted elements into the varistor during firing. Various elements are added to control shrinkage. In addition, a buffer layer is inserted in the middle of the varistor-capacitor junction to prevent diffusion during firing, thereby developing a co-fired product with desirable characteristics.
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