A Parallel Search Algorithm and Its Implementation for Digital k-Winners-Take-All Circuit

Yoon, Myungchul The Institute of Electronics and Information Engin 2015 Journal of semiconductor technology and science Vol.15 No.4

The k-Winners-Take-All (kWTA) is an operation to find the largest k (>1) inputs among N inputs. Parallel search algorithm of kWTA for digital inputs is not invented yet, so most of digital kWTA architectures have O(N) time complexity. A parallel search algorithm for digital kWTA operation and the circuits for its VLSI implementation are presented in this paper. The proposed kWTA architecture can compare all inputs simultaneously in parallel. The time complexity of the new architecture is O(logN), so that it is scalable to a large number of digital data. The high-speed kWTA operation and its O(logN) dependency of the new architecture are verified by simulations. It takes 290 ns in searching for 5 winners among 1024 of 32 bit data, which is more than thousands of times faster than existing digital kWTA circuits, as well as existing analog kWTA circuits.

A VLSI Design for Scalable High-Speed Digital Winner-Take-All Circuit

Myungchul Yoon 대한전자공학회 2015 Journal of semiconductor technology and science Vol.15 No.2

A high speed VLSI digital Winner-Take-All (WTA) circuit called simultaneous digital WTA (SDWTA) circuit is presented in this paper. A minimized comparison-cell (w-cell) is developed to reduce the size and to achieve high-speed. The w-cell which is suitable for VLSI implementation consists of only four transistors. With a minimized comparison cell structure SDWTA can compare thousands of data simultaneously. SDWTA is scalable with O(mlog n) time-complexity for n of m-bit data. According to simulations, it takes 16.5 ns with 1.2V-0.13 mm process technology in finding a winner among 1024 of 16-bit data.

A VLSI Design for Scalable High-Speed Digital Winner-Take-All Circuit

Yoon, Myungchul The Institute of Electronics and Information Engin 2015 Journal of semiconductor technology and science Vol.15 No.2

A high speed VLSI digital Winner-Take-All (WTA) circuit called simultaneous digital WTA (SDWTA) circuit is presented in this paper. A minimized comparison-cell (w-cell) is developed to reduce the size and to achieve high-speed. The w-cell which is suitable for VLSI implementation consists of only four transistors. With a minimized comparison-cell structure SDWTA can compare thousands of data simultaneously. SDWTA is scalable with O(mlog n) time-complexity for n of m-bit data. According to simulations, it takes 16.5 ns with $1.2V-0.13{\mu}m$ process technology in finding a winner among 1024 of 16-bit data.

A Parallel Search Algorithm and Its Implementation for Digital k-Winners-Take-All Circuit

Myungchul Yoon 대한전자공학회 2015 Journal of semiconductor technology and science Vol.15 No.4

The k-Winners-Take-All (kWTA) is an operation to find the largest k (>1) inputs among N inputs. Parallel search algorithm of kWTA for digital inputs is not invented yet, so most of digital kWTA architectures have O(N) time complexity. A parallel search algorithm for digital kWTA operation and the circuits for its VLSI implementation are presented in this paper. The proposed kWTA architecture can compare all inputs simultaneously in parallel. The time complexity of the new architecture is O(logN), so that it is scalable to a large number of digital data. The high-speed kWTA operation and its O(logN) dependency of the new architecture are verified by simulations. It takes 290 ns in searching for 5 winners among 1024 of 32 bit data, which is more than thousands of times faster than existing digital kWTA circuits, as well as existing analog kWTA circuits.

A Novel Architecture of Asynchronous Sorting Engine Module for ASIC Design

Myungchul Yoon 대한전자공학회 2022 Journal of semiconductor technology and science Vol.22 No.4

A novel sorting engine called Sorting Grid (SG) is presented in this paper. SG is intended to be used as a hardware module for ASIC design which can be employed for any ASIC chip requiring fast sorting operation. The SG is implemented by simple modular architecture so that it is easily synthesized with conventional ASIC tools. SG allows inputs with the same key and provides stable sorting for those inputs. SG sorts m-bit N binary inputs in (m+1) cycles with variable cycle time. SG employs a self-timed asynchronous clock of which the period changes according to the operation time of each cycle. The clock period greatly decreases along the cycle. With this clock and a multi-level bypassing scheme, SG has O(N+m) time-complexity for pseudo-random binary inputs. By the simulations with 1.2V-0.13 μm process technology, the sorting rate of the SG is about 1 ns per input for 16-bit inputs.

A Fast (7, 3)-adder Circuit for High-speed Multiplier Design

Myungchul Yoon 대한전자공학회 2022 IEIE Transactions on Smart Processing & Computing Vol.11 No.4

A set of fast (m, 3)-adder circuits (4 ≤ m ≤ 7) is presented in this paper. An (m, 3)-adder adds m bits at a time and produces three outputs (N, C, S). These adders are designed to implement high-speed (7, 3)-adder based multipliers that use a (7, 3)-adder as a basic unit and five other adders ((6, 3), (5, 3), (4, 3), (3, 2), and (2, 2)-adder) as auxiliary units for the addition of partial products. Multipliers require adding tens of partial products to obtain a result, and they can be added by (7, 3)-adders more quickly than by (3, 2)-adders. In simulation results, the worst-case delay and power of the new (7, 3)-adder are 1.45 times and 2.4 times larger than those of the reference (3, 2)-adder. However, the parallel addition of partial products with the (7, 3)-adder is faster and consumes less power than with the (3, 2)-adder because the (7, 3)-adder based multiplier requires fewer adders and addition stages than a (3, 2)-adder based multiplier. This result shows that the speed of a multiplier can be increased by using (7, 3)-adders instead of (3, 2)-adders in reducing partial products.

A Two-bit Bus-Invert Coding Scheme With a Mid-level State Bus-Line for Low Power VLSI Design

Yoon, Myungchul The Institute of Electronics and Information Engin 2014 Journal of semiconductor technology and science Vol.14 No.4

A new bus-invert coding circuit, called Two-bit Bus-Invert Coding (TBIC) is presented. TBIC partitions a bus into a set of two-bit sub-buses, and applies the bus-invert (BI) algorithm to each sub-bus. Unlike ordinary BI circuits using invert-lines, TBIC does not use an invert-line, so that it sends coding information through a bus-line. To transmit 3-bit information with 2 bus-lines, TBIC allows one bus-line to have a mid-level state, called M-state. TBIC increases the performance of BI algorithm, by suppressing the generation of overhead transitions. TBIC reduces bus transitions by about 45.7%, which is 83% greater than the maximum achievable performance of ordinary BI with invert-lines.

내부 트리거 발생회로를 이용한 고속의 디지털 Maximum Selector 회로의 설계

윤명철(Myungchul Yoon) 大韓電子工學會 2011 電子工學會論文誌-SD (Semiconductor and devices) Vol.48 No.2

그동안 신경망칩의 설계에는 주로 아날로그 Maximum Selector (MS) 회로를 사용하였다. 그러나 집적도가 높아질수록 아날로그 MS회로는 신호의 해상도(Resolution)을 높이는데 어려움이 있다. 반면 디지털 MS 회로는 높은 해상도를 얻기는 쉬우나 속도가 느린 단점이 있었다. 본 논문에서는 신경망칩의 디지털화에 사용하기 위한 MSIT(Maximum Selector with Internal Trigger-Signal) 라는 고속의 디지털 MS회로를 개발하였다. MSIT는 제어신호 발생기를 내장하여 안정적인 동작을 확보하고, 불필요한 대기시간을 없애도록 이를 최적화 함으로써 높은 속도를 얻을 수 있다. 1.2V-0.13㎛ 프로세스의 모델파라메터를 사용하여 32 개의 10 비트 데이터에 대하여 시뮬레이션을 수행한 결과 3.4㎱의 응답시간을 얻을 수 있었다. 이는 동급의 해상도를 갖는 아날로그 MS회로 보다 훨씬 빠른 속도로써, MSIT와 같은 디지털 MS 회로가 아날로그 MS회로에 비하여 높은 해상도와 빠른 속도를 구현할 수 있음을 보여준다. Most of neural network chips use an analog-type maximum selector circuit (MS). As the increase of integration level, the analog MS has difficulties in achieving sufficient resolution. Contrary, the digital-type MS is easy to get high resolution but slower than its analog counterparts. A new high-speed digital MS circuit called MSIT (Maximum Selector with Internal Trigger-signal) is presented in this paper. The MSIT has been designed to achieves both the high reliability by using trigger-signals and high speed by removing the unnecessary waiting times. The response time of MSIT is 3.4㎱ for 32 data with 10-bit resolution in the simulation with 1.2V, 0.13㎛-process model parameters, which is much faster than its analog counterparts. It shows that digital MS circuits like MSIT can achieve higher speed as well as higher resolution than analog MS circuits.

보조선을 사용하지 않은 Sequence Switch Coding 회로의 설계

윤명철(Myungchul Yoon) 大韓電子工學會 2009 電子工學會論文誌-SD (Semiconductor and devices) Vol.46 No.11

코딩정보의 전송을 위하여 보조선에서 발생하는 오버헤드전이는 Sequence Switching Code (SSC) 알고리즘의 확장성을 제한하는 가장 큰 걸림돌이 되어왔다. 본 논문에서는 보조선을 사용하지 않고 SSC 회로를 구현하는 방법과 함께 이 방법을 사용하여 보조선을 사용하였을 때 보다 오버헤드전이를 적게 발생시키는 방법을 제시하였다. 실험결과 새로운 방법을 적용함으로써 보조선을 사용하는 방식에 비하여 오버헤드전이의 발생을 50% 이하로 줄이고 알고리즘의 효율을 약 30% 향상시킬 수 있었다. The transition of auxiliary lines for transmitting coding information has been one of the major obstacles to restricting the scalability of Sequence Switch Coding (SSC) algorithms. A new design of SSC which does not use auxiliary lines is presented in this paper. The new design makes overhead transitions far less than the previous designs that use auxiliary lines. By applying the new technique, more than 50% of overhead transitions have been reduced, leading to the increase of 30% of the overall efficiency of SSC algorithm.

A Comparative Evaluation of Radiation-Induced DNA Damage using Real-Time PCR: Influence of Base Composition

Lim, Sangyong,Yoon, Hyunjin,Ryu, Sangryeol,Jung, Jinwoo,Lee, Myungchul,Kim, Dongho Academic Press 2006 Radiation research Vol.165 No.4

Lim, S., Yoon, H., Ryu, S., Jung, J., Lee, M. and Kim, D. A Comparative Evaluation of Radiation-Induced DNA Damage using Real-Time PCR: Influence of Base Composition. Radiat. Res. 165, 430??437 (2006).To study the radiosensitivity of DNA segments at the open reading frame (gene) level, real-time PCR was used to analyze DNA damages induced by ionizing radiation. After irradiation (1, 3 and 5 kGy) of genomic DNA purified from Salmonella typhimurium, real-time PCR based on SYBR Green fluorescence and melting temperature was performed using various primer sets targeting the rfbJ, rfaJ, rfaB, hilD, ssrB, pipB, sopD, pduQ, eutG, oadB, ccmB and ccmA genes. The ccmA and ccmB genes, which existed as two copies on the chromosome and had a high GC content (??0%), showed much lower radiosensitivities than the other genes tested, particularly at 5 kGy; this distinctive feature was seen only when the genes were located on the chromosome, regardless of copy number. Our results reinforce the concept that gene sensitivity to ionizing radiation depends on the base composition and/or the spatial localization of the gene on the chromosome.